The Effectiveness of Numbered Heads Together in Teaching Readingviewed From Students' Locus of Control

This writing applied an experimental design. The population of the research was the eighth graders of Senior High School academic year of 2011/2012 consisting of three classes. Two out of the three classes, consisting of 40 students, were used as the sample using the technique of cluster random sampling. The experimental group was taught using the NHT strategy, while the control group using expository strategy. A questionnaire and test of reading were used to collect the research data. The result of analysis shows that NHT is proved as an effective teaching strategy to teach reading for the eighth grade. The effectiveness is affected by students' level of Locus of Control

An Analysis of a Harmonization of Homo Ludens and Homo Faber for Academics as a Recommendation for Incubation Facility Design in a Staffs Room

Humans work to meet their basic needs for living. In anthropology, there is a term Homo Faber, which means that humans work and refers to the human ability to control their destiny and what surrounds them. Individuals who are less able to adapt to the demands of work they receive, ultimately cause stress on themselves. Because in essence humans are also Homo Ludens which is referring to humans as players and play. An activity that is considered to cause pleasure and release stress. The need to harmonize individual activities as Homo Faber and Homo Ludens, and to support the needs of the incubation phase in creative processes for academics is the focused discussion in this study. Telkom University Product Design Lecturers are the informants of research in this paper. Case Study is the research methodology that is applied in this paper. Which this study is expected to produce a recommendation for the design of incubation facilities for Product Design Lecturers who are tailored to the needs and characteristics of the incubation activities carried out by the Lecturers. The purpose of this study is expected that could help the performance development in pace work of the Design Lecturers. Keywords Characteristic Analysis, Creative Process, Incubation Facility, Work Cultur

On vv--domains and star operations

Let $\ast$ be a star operation on an integral domain $D$. Let \f(D) be the set of all nonzero finitely generated fractional ideals of $D$. Call $D$ a $\ast$--Pr\"ufer (respectively, $(\ast, v)$--Pr\"ufer) domain if $(FF^{-1})^{\ast}=D$ (respectively, $(F^vF^{-1})^{\ast}=D$) for all F\in \f(D). We establish that $\ast$--Pr\"ufer domains (and $(\ast, v)$--Pr\"ufer domains) for various star operations $\ast$ span a major portion of the known generalizations of Pr\"{u}fer domains inside the class of $v$--domains. We also use Theorem 6.6 of the Larsen and McCarthy book [Multiplicative Theory of Ideals, Academic Press, New York--London, 1971], which gives several equivalent conditions for an integral domain to be a Pr\"ufer domain, as a model, and we show which statements of that theorem on Pr\"ufer domains can be generalized in a natural way and proved for $\ast$--Pr\"ufer domains, and which cannot be. We also show that in a $\ast$--Pr\"ufer domain, each pair of $\ast$-invertible $\ast$-ideals admits a GCD in the set of $\ast$-invertible $\ast$-ideals, obtaining a remarkable generalization of a property holding for the "classical" class of Pr\"ufer $v$--multiplication domains. We also link $D$ being $\ast$--Pr\"ufer (or $(\ast, v)$--Pr\"ufer) with the group Inv$^{\ast}(D)$ of $\ast$-invertible $\ast$-ideals (under $\ast$-multiplication) being lattice-ordered

Dynamic Graphs on the GPU

We present a fast dynamic graph data structure for the GPU. Our dynamic graph structure uses one hash table per vertex to store adjacency lists and achieves 3.4–14.8x faster insertion rates over the state of the art across a diverse set of large datasets, as well as deletion speedups up to 7.8x. The data structure supports queries and dynamic updates through both edge and vertex insertion and deletion. In addition, we define a comprehensive evaluation strategy based on operations, workloads, and applications that we believe better characterize and evaluate dynamic graph data structures

A Critical Review of Recent Progress on Negative Capacitance Field-Effect Transistors

The elegant simplicity of the device concept and the urgent need for a new "transistor" at the twilight of Moore's law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance field effect transistor (NC-FET). Although hundreds of papers have been published, the validity of quasi-static NC and the frequency-reliability limits of NC-FET are still being debated. The concept of NC - if conclusively demonstrated - will have broad impacts on device physics and technology development. Here, the authors provide a critical review of recent progress on NC-FETs research and some starting points for a coherent discussion.Comment: 19 pages, 2 figure

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Estimating a Demand System with Seasonally Differenced Data

Researchers estimating demand systems have often used annual data even though monthly or quarterly data are available. Monthly data may be avoided because with monthly data it becomes more difficult to specify seasonality, autocorrelation is more likely to be significant, and there is a greater chance of finding significant dynamics in demand. This paper shows how to obtain consistent and asymptotically efficient estimates of a demand system using seasonal differenced data. It also shows that several alternative estimators are either inefficient or implausible for demand systems.Demand and Price Analysis,

A bridgeless Cuk PFC converter

A bridgeless Power Factor Correction (PFC) circuit based on Cuk converter is proposed in this paper. The operation during each sub-interval modes of the converter operated in Discontinuous Conduction Mode (DCM) is discussed. The smallsignal and large signal models are presented using Current Injected Equivalent Circuit Approach (CIECA). PLECS/Simulink is used to verify the capability of the proposed converter to regulate the output voltage while the input current regulation is inherent. This converter is capable to operate in universal input voltage condition