Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations

Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures

Data Quality Automation: a Generic Approach for Large Linked Research Datasets

Introduction When datasets are collected mainly for administrative rather than research purposes, data quality checks are necessary to ensure robust findings and to avoid biased results due to incomplete or inaccurate data. When done manually, data quality checks are time-consuming. We introduced automation to speed up the process and save effort. Objectives and Approach We have devised a set of automated generic quality checks and reporting, which can be run on any dataset in a relational database without any dataset-specific knowledge or configuration. The code is written in Python. Checks include: linkage quality, agreement with a population data source, comparison with previous data version, duplication checks, null count, value distribution and range, etc. Where dataset metadata is available, checks for validity against lookup tables are included, and the output report includes documentation on data contents. An HTML report with dynamic datatables and interactive graphs, allowing easy exploration of the results, is produced using RMarkdown. Results The automation of the generic data quality check provides an easy and quick tool to report on data issues with minimal effort. It allows comparison with reference tables, lookups and previous versions of the same table to highlight differences. Moreover, this tool can be provided for researchers as a means to get more detailed understanding about their data. While other research data quality tools exist, this tool is distinguished by its features specific to linked data research, as well as implementation in a relational database environment. It has been successfully tested on datasets of over two billion rows. The tool was designed for use within the SAIL Databank, but could easily be adapted and used in other settings. Conclusion/Implications The effort spent on automating generic testing and reporting on data quality of research datasets is more than compensated by its outputs. Benefits include quick detection and scrutiny of many sources of invalid and incomplete data. This process can easily be expanded to accommodate more standard tests

Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs

The fin-edge roughness (FER) and the TiN metal grain work function (MGW)-induced variability affecting OFF and ON device characteristics are studied and compared between a 10.4 nm gate length In0.53Ga0.47As FinFET and a 10.7 nm gate length Si FinFET. We have analyzed the impact of variability by assessing five figures of merit (threshold voltage, subthreshold slope, OFF-current, drain-induced-barrier-lowering, and ON-current) using the two state-of-the-art in-house-build 3-D simulation tools based on the finite-element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the subthreshold region while, in the ON-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In0.53Ga0.47As FinFET is more resilient to the FER and MGW variability in the subthreshold compared with the Si FinFET due to a stronger quantum carrier confinement present in the In0.53Ga0.47As channel. However, the ON-current variability is between 1.1 and 2.2 times larger for the In0.53Ga0.47As FinFET than for the Si counterpart, respectively

Anisotropic Quantum Corrections for 3-D Finite-Element Monte Carlo Simulations of Nanoscale Multigate Transistors

Anisotropic 2-D Schrödinger equation-based quantum corrections dependent on valley orientation are incorporated into a 3-D finite-element Monte Carlo simulation toolbox. The new toolbox is then applied to simulate nanoscale Si Siliconon-Insulator FinFETs with a gate length of 8.1 nm to study the contributions of conduction valleys to the drive current in various FinFET architectures and channel orientations. The 8.1 nm gate length FinFETs are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: 〈100〉 and 〈110〉. We have found that quantum anisotropy effects play the strongest role in the triangular-like 〈100〉 channel device increasing the drain current by ~13% and slightly decreasing the current by 2% in the rectangular-like 〈100〉 channel device. The quantum anisotropy has a negligible effect in any device with the 〈110〉 channel orientation

3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte Carlo (MC) simulations with 2D Schroedinger equation quantum corrections. These non-planar transistors are studied for two cross-sections: rectangular-like and triangular-like, and for two channel orientations: h100i and h110i. The 10.7 nm gate length rectangular-like FinFET is also simulated using the 3D Non-Equilibrium Green’s Functions (NEGF) technique and the results are compared with MC simulations. The 12.8 nm and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 25−27% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a <100> channel orientation deliver a larger drive current by about 11% than their counterparts with a h110i channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID–VG characteristics at low and high drain biases obtained from the 3D NEGF simulations show a remarkable agreement with the MC results and overestimate the drain current from a gate bias of 0.5 V only due to exclusion of the interface roughness and ionized impurity scatterings

Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs

Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer-aided simulations in order to aid future device designs. Quantum corrected (QC) drift-diffusion (DD) simulations are usually employed to estimate the variability of state-of-the-art non-planar devices but require meticulous calibration. More accurate simulation methods, such as QC Monte Carlo (MC), are considered time consuming and elaborate. Therefore, we predict TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability on a 10-nm gate length gate-all-around Si nanowire FET and perform a rigorous comparison of the QC DD and MC results. In case of the MGG, we have found that the QC DD predicted variability can have a difference of up to 20% in comparison with the QC MC predicted one. In case of the LER, we demonstrate that the QC DD can overestimate the QC MC simulation produced variability by a significant error of up to 56%. This error between the simulation methods will vary with the root mean square (RMS) height and maximum source/drain n -type doping. Our results indicate that the aforementioned QC DD simulation technique yields inaccurate results for the ON-current variability

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

The fin-edge roughness and the TiN metal grain work function-induced variability affecting device characteristics are studied and compared between a 10.4-nm gate length In0.53Ga0.47As FinFET and a 10.7-nm gate length Si FinFET. We have analysed the impact of variability by looking on five figures of merit (threshold voltage, sub-threshold slope, off-current, DIBL, and on-current) using the two state-of-the-art in-house-build 3-D simulation tools based on the finite-element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the sub-threshold region while, in the ON-rwillegion, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In0.53Ga0.47As FinFET is more resistant to the fin-edge roughness and metal grain work function variability in the sub-threshold compared with the Si FinFET due to a stronger quantum carrier confinement present in the In0.53Ga0.47As channel. However, the ON-current variability is between 1.1 and 2.2 times larger for the In0.53Ga0.47As FinFET than for the Si transistor, respectively.wil

SwanseaUniversityMedical/concept-library: Concept-Library-2.0.13

<h2><a href="https://github.com/SwanseaUniversityMedical/concept-library/compare/Concept-Library-2.0.12...Concept-Library-2.0.13">2.0.13</a> (2023-11-10)</h2&gt

SwanseaUniversityMedical/concept-library: Concept-Library-2.0.11

<h2><a href="https://github.com/SwanseaUniversityMedical/concept-library/compare/Concept-Library-2.0.10...Concept-Library-2.0.11">2.0.11</a> (2023-11-07)</h2&gt