Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges

Physics-inspired End-to-End Deep Learning for High-Performance Optical Fiber Transmission Links

We experimentally demonstrate the performance improvements obtained through End-to-End Deep Learning in noise and chromatic dispersion compensation of optical fiber transmission links when incorporating a physics-inspired activation function compared to state-of-the-art ReLU configurations

Broadband 5Gb/s optical RAM cell over the C-band

A broadband optical RAM cell comprising a monolithic InP Flip-Flop and a Random Access Gate is experimentally presented with at least 5 Gb/s error-free operation and less than 4.5dB power penalty across the whole C-band

Noise-resilient and high-speed deep learning with coherent silicon photonics

The explosive growth of deep learning applications has triggered a new era in computing hardware, targeting the efficient deployment of multiply-and-accumulate operations. In this realm, integrated photonics have come to the foreground as a promising energy efficient deep learning technology platform for enabling ultra-high compute rates. However, despite integrated photonic neural network layouts have already penetrated successfully the deep learning era, their compute rate and noise-related characteristics are still far beyond their promise for high-speed photonic engines. Herein, we demonstrate experimentally a noise-resilient deep learning coherent photonic neural network layout that operates at 10GMAC/sec/axon compute rates and follows a noise-resilient training model. The coherent photonic neural network has been fabricated as a silicon photonic chip and its MNIST classification performance was experimentally evaluated to support accuracy values of &gt;99% and &gt;98% at 5 and 10GMAC/sec/axon, respectively, offering 6× higher on-chip compute rates and &gt;7% accuracy improvement over state-of-the-art coherent implementations.</p