Smart camera with embedded co-processor: a postal sorting application

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, multi-exposition image) as well as high-performance image pre-processing (filtering, de-noising, binarisation, pattern recognition). Furthermore, the acquisition is driven by an FPGA, as well as a processing stage followed by a Nexperia processor. The data transfer, from the FPGAs board to the Nexperia processor, can be pipelined to the co-processor to increase achievable throughput performances. The co-processor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing (up to 8 successive pre-defined pre-processing), during the image acquisition process that is dynamically defined by the application. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the performances. For instance the reading of bar codes with applications to postal sorting on a PC platform is limited to about 15 images (letters) per second. The new platform beside resulting more compact and easily installable in hostile environments can successfully analyze up to 50 images/s

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

This paper presents a contribution to the development of rapid prototyping tools based on data-flow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cases. Moreover, this paper presents the novel concept of the automatic synthesis of interfaces based on dataflow description. Such “generic” interfaces include an embedded microprocessor, which enables using a vide variety of interfaces already available as optimized libraries from the FPGA manufacturers. The different design cases described have been tested and validated on different platforms. The results of the work show the flexibility and generality of the proposed wrapper methodology that is described in the paper

High-speed smart camera with high resolution

International audienc

Compression embarquée temps réel pour caméras rapides

Les caméras rapides sont de puissants outils pour étudier, par exemple, la dynamique des fluides ou le déplacement des pièces mécaniques lors d'un processus de fabrication. Nous décrivons dans ce papier, un nouveau type de caméra rapide possédant un fonctionnement original. En effet, outre le fait qu'elle utilise comme d'autres caméras, la grande flexibilité des capteurs CMOS en termes d'acquisition (ROI), elle est novatrice au niveau du transfert des données. Celles-ci pouvant être à la fois traitées et/ou compressées en temps réel au sein même de la caméra. Le transfert peut s'effectuer alors à l'aide d'une simple connection série de type USB 2.0. On réalise ainsi l'économie d'une mémoire embarquée, les données étant directement stockées sur la mémoire d'un PC standard, ce qui permet d'utiliser l'intégralité de ses capacités (grande taille mémoire, évolution constante). En parallèle au développement matérielle de la caméra, nous présenterons les algorithmes de compression intégrés au sein de la caméra, notamment un algorithme nous permettant d'utiliser la caméra à sa plus grande résolution (1280 x 1024 pixels) et avec une fréquence image de 500 par seconde. Son taux de compression est de 20, avec un PSNR supérieur `a 30

Smart Camera Based on Embedded HW/SW Coprocessor

This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is integrated into the image acquisition loop. The acquisition and coprocessing architecture are compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes as well as the reconfiguration and implementation of high-performance image preprocessing algorithms (calibration, filtering, denoising, binarization, pattern recognition). Furthermore, the processing and data transfer, from the CMOS sensor to the processor, can be operated simultaneously to increase achievable performances. The coprocessor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing stages (up to 8 successive predefined preprocessing stages), during the image acquisition process that can be defined by the user according to each specific application requirement. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the achievable performances

Generation of Hardware/Software systems based on CAL dataflow description

International audienceThis paper presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The paper also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results of the assessment show that flexibility, genericity and generality are attractive features of the proposed interface implementation methodology approach