111 research outputs found
Alberdi Reader of Tocqueville, or the Possible Liberalism: Theory and Practice of Politics in 19th Century Argentina
El artĂculo se propone analizar la influencia de La democracia en AmĂ©rica de Alexis de Tocqueville en el pensamiento constitucional de Juan Bautista Alberdi. Desde un abordaje histĂłrico intelectual, señalaremos las lecturas que Alberdi realizĂł de esta obra de Tocqueville, y el modo en que estas impactaron a su tiempo en su proyecto constitucional para la ConfederaciĂłn Argentina. A estos fines, restituiremos las principales caracterĂsticas de la nueva ciencia polĂtica de Tocqueville, para luego analizar el modo en que el mĂ©todo de Tocqueville y sus corolarios sociolĂłgico-polĂticos conducen a Alberdi a propugnar por una peculiar adaptaciĂłn del sistema federal estadounidense, en vistas de un objetivo econĂłmico que estaba lejos de las preocupaciones cardinales del francĂ©s. Nuestra hipĂłtesis es que Alberdi extrajo del Tocqueville que alcanzĂł a conocer un mĂ©todo y una serie de advertencias y corolarios respecto del desarrollo de la democracia y de la libertad en AmĂ©rica del Sur.The purpose of this article is to analyze the influence of Alexis de Tocqueville's Democracy in America on the constitutional thought of Juan Bautista Alberdi. From a historical-intellectual approach, we will point out Alberdi's readings of Tocqueville's work, and the way in which them had an impact on his constitutional project for the Argentine Confederation. To this end, we will summarily restitute the main characteristics of the new political science advocated by Tocqueville, and then analyze the way in which Tocqueville's method and its sociological-political corollaries lead Alberdi to advocate a peculiar adaptation of the American federal system, in view of an economic objective that was far from the Frenchman's cardinal concerns. Our hypothesis is that Alberdi drew from the Tocqueville he came to know a method and a series of warnings and corollaries regarding the development of democracy and liberty in South America.Fil: Morán, Sabrina. Consejo Nacional de Investigaciones CientĂficas y TĂ©cnicas; Argentina. Universidad de Buenos Aires. Facultad de Ciencias Sociales. Instituto de Investigaciones "Gino Germani". Area TeorĂa PolĂtica; ArgentinaFil: Wieczorek, Tomás. Consejo Nacional de Investigaciones CientĂficas y TĂ©cnicas; Argentina. Universidad de Buenos Aires. Facultad de Ciencias Sociales. Instituto de Investigaciones "Gino Germani". Area TeorĂa PolĂtica; Argentin
Fault Modeling of Graphene Nanoribbon FET Logic Circuits
[EN] Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.This work was supported in part by the Spanish Government under the research project TIN2016-81075-R and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), under the project 200190032.Gil Tomás, DA.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil, P. (2019). Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics. 8(8):1-18. https://doi.org/10.3390/electronics8080851S11888International Technology Roadmap for Semiconductors (ITRS) 2013http://www.itrs2.net/2013-itrs.htmlSchuegraf, K., Abraham, M. C., Brand, A., Naik, M., & Thakur, R. (2013). Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing. IEEE Journal of the Electron Devices Society, 1(3), 66-75. doi:10.1109/jeds.2013.2271582International Technology Roadmap for Semiconductors (ITRS) 2015https://bit.ly/2xiiT8PNovoselov, K. S. (2004). Electric Field Effect in Atomically Thin Carbon Films. Science, 306(5696), 666-669. doi:10.1126/science.1102896Geim, A. K., & Novoselov, K. S. (2007). The rise of graphene. Nature Materials, 6(3), 183-191. doi:10.1038/nmat1849Wu, Y., Farmer, D. B., Xia, F., & Avouris, P. (2013). Graphene Electronics: Materials, Devices, and Circuits. Proceedings of the IEEE, 101(7), 1620-1637. doi:10.1109/jproc.2013.2260311Choudhury, M. R., Youngki Yoon, Jing Guo, & Mohanram, K. (2011). Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability. IEEE Transactions on Nanotechnology, 10(4), 727-736. doi:10.1109/tnano.2010.2073718Avouris, P. (2010). Graphene: Electronic and Photonic Properties and Devices. Nano Letters, 10(11), 4285-4294. doi:10.1021/nl102824hBanadaki, Y. M., & Srivastava, A. (2015). Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology. IEEE Transactions on Emerging Topics in Computing, 3(4), 458-469. doi:10.1109/tetc.2015.2445104Avouris, P., Chen, Z., & Perebeinos, V. (2007). Carbon-based electronics. Nature Nanotechnology, 2(10), 605-615. doi:10.1038/nnano.2007.300Banerjee, S. K., Register, L. F., Tutuc, E., Basu, D., Kim, S., Reddy, D., & MacDonald, A. H. (2010). Graphene for CMOS and Beyond CMOS Applications. Proceedings of the IEEE, 98(12), 2032-2046. doi:10.1109/jproc.2010.2064151Schwierz, F. (2013). Graphene Transistors: Status, Prospects, and Problems. Proceedings of the IEEE, 101(7), 1567-1584. doi:10.1109/jproc.2013.2257633Fregonese, S., Magallo, M., Maneux, C., Happy, H., & Zimmer, T. (2013). Scalable Electrical Compact Modeling for Graphene FET Transistors. IEEE Transactions on Nanotechnology, 12(4), 539-546. doi:10.1109/tnano.2013.2257832Chen, Y.-Y., Sangai, A., Rogachev, A., Gholipour, M., Iannaccone, G., Fiori, G., & Chen, D. (2015). A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation. IEEE Transactions on Nanotechnology, 14(6), 1068-1082. doi:10.1109/tnano.2015.2469647Ferrari, A. C., Bonaccorso, F., Fal’ko, V., Novoselov, K. S., Roche, S., Bøggild, P., … Pugno, N. (2015). Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems. Nanoscale, 7(11), 4598-4810. doi:10.1039/c4nr01600aHong, A. J., Song, E. B., Yu, H. S., Allen, M. J., Kim, J., Fowler, J. D., … Wang, K. L. (2011). Graphene Flash Memory. ACS Nano, 5(10), 7812-7817. doi:10.1021/nn201809kJeng, S.-L., Lu, J.-C., & Wang, K. (2007). A Review of Reliability Research on Nanotechnology. IEEE Transactions on Reliability, 56(3), 401-410. doi:10.1109/tr.2007.903188Srinivasu, B., & Sridharan, K. (2017). A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies. IEEE Transactions on Reliability, 66(2), 440-457. doi:10.1109/tr.2016.2642168Teixeira Franco, D., Naviner, J.-F., & Naviner, L. (2006). Yield and reliability issues in nanoelectronic technologies. annals of telecommunications - annales des télécommunications, 61(11-12), 1422-1457. doi:10.1007/bf03219903Lin, Y.-M., Jenkins, K. A., Valdes-Garcia, A., Small, J. P., Farmer, D. B., & Avouris, P. (2009). Operation of Graphene Transistors at Gigahertz Frequencies. Nano Letters, 9(1), 422-426. doi:10.1021/nl803316hLiao, L., Lin, Y.-C., Bao, M., Cheng, R., Bai, J., Liu, Y., … Duan, X. (2010). High-speed graphene transistors with a self-aligned nanowire gate. Nature, 467(7313), 305-308. doi:10.1038/nature09405Wang, X., Tabakman, S. M., & Dai, H. (2008). Atomic Layer Deposition of Metal Oxides on Pristine and Functionalized Graphene. Journal of the American Chemical Society, 130(26), 8152-8153. doi:10.1021/ja8023059Geim, A. K. (2009). Graphene: Status and Prospects. Science, 324(5934), 1530-1534. doi:10.1126/science.1158877Mistewicz, K., Nowak, M., Wrzalik, R., Śleziona, J., Wieczorek, J., & Guiseppi-Elie, A. (2016). Ultrasonic processing of SbSI nanowires for their application to gas sensors. Ultrasonics, 69, 67-73. doi:10.1016/j.ultras.2016.04.004Jesionek, M., Nowak, M., Mistewicz, K., Kępińska, M., Stróż, D., Bednarczyk, I., & Paszkiewicz, R. (2018). Sonochemical growth of nanomaterials in carbon nanotube. Ultrasonics, 83, 179-187. doi:10.1016/j.ultras.2017.03.014Chen, X., Seo, D. H., Seo, S., Chung, H., & Wong, H.-S. P. (2012). Graphene Interconnect Lifetime: A Reliability Analysis. IEEE Electron Device Letters, 33(11), 1604-1606. doi:10.1109/led.2012.2211564Wang, Z. F., Zheng, H., Shi, Q. W., & Chen, J. (2009). Emerging nanodevice paradigm. ACM Journal on Emerging Technologies in Computing Systems, 5(1), 1-19. doi:10.1145/1482613.1482616Dong, J., Xiang, G., Xiang-Yang, K., & Jia-Ming, L. (2007). Atomistic Failure Mechanism of Single Wall Carbon Nanotubes with Small Diameters. Chinese Physics Letters, 24(1), 165-168. doi:10.1088/0256-307x/24/1/045Bu, H., Chen, Y., Zou, M., Yi, H., Bi, K., & Ni, Z. (2009). Atomistic simulations of mechanical properties of graphene nanoribbons. Physics Letters A, 373(37), 3359-3362. doi:10.1016/j.physleta.2009.07.04
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
© 2018 IEEE. Personal use of this material is permitted. PermissĂon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisĂng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] Currently, faults suffered by SRAM memory
systems have increased due to the aggressive CMOS integration
density. Thus, the probability of occurrence of single-cell
upsets (SCUs) or multiple-cell upsets (MCUs) augments. One
of the main causes of MCUs in space applications is cosmic
radiation. A common solution is the use of error correction
codes (ECCs). Nevertheless, when using ECCs in space applications,
they must achieve a good balance between error coverage
and redundancy, and their encoding/decoding circuits must be
efficient in terms of area, power, and delay. Different codes have
been proposed to tolerate MCUs. For instance, Matrix codes use
Hamming codes and parity checks in a bi-dimensional layout to
correct and detect some patterns of MCUs. Recently presented,
columnÂżlineÂżcode (CLC) has been designed to tolerate MCUs
in space applications. CLC is a modified Matrix code, based
on extended Hamming codes and parity checks. Nevertheless,
a common property of these codes is the high redundancy
introduced. In this paper, we present a series of new lowredundant
ECCs able to correct MCUs with reduced area, power,
and delay overheads. Also, these new codes maintain, or even
improve, memory error coverage with respect to Matrix and
CLC codes.This work was supported by the Spanish Government under the research Project TIN2016-81075-R.Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(10):2132-2142. https://doi.org/10.1109/TVLSI.2018.2837220S21322142261
Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor
© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.This work was supported by the Spanish Government under the Research Project TIN2009-13825 and by the Universitat Politecnica de Valencia under the Project SP20120806. Associate Editor: L. Cui.Gracia-Morán, J.; Baraza Calvo, JC.; Gil Tomás, DA.; Saiz-Adalid, L.; Gil, P. (2014). Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor. IEEE Transactions on Reliability. 63(1):144-153. https://doi.org/10.1109/TR.2014.2299711S14415363
Reducing the Overhead of BCH Codes: New Double Error Correction Codes
[EN] The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors.This research was supported in part by the Spanish Government, project TIN2016-81075-R, by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032, and by the Institute of Information and Communication Technologies (ITACA).Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2020). Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics. 9(11):1-14. https://doi.org/10.3390/electronics9111897S114911Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748Xinmiao, Z. (2017). VLSI Architectures for Modern Error-Correcting Codes. doi:10.1201/b18673Bose, R. C., & Ray-Chaudhuri, D. K. (1960). On a class of error correcting binary group codes. Information and Control, 3(1), 68-79. doi:10.1016/s0019-9958(60)90287-4Chen, P., Zhang, C., Jiang, H., Wang, Z., & Yue, S. (2015). High performance low complexity BCH error correction circuit for SSD controllers. 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). doi:10.1109/edssc.2015.7285089IEEE 802.3-2018 - IEEE Standard for Ethernethttps://standards.ieee.org/standard/802_3-2018.htmlH.263: Video Coding for Low Bit Rate Communicationhttps://www.itu.int/rec/T-REC-H.263/enVangelista, L., Benvenuto, N., Tomasin, S., Nokes, C., Stott, J., Filippi, A., … Morello, A. (2009). Key technologies for next-generation terrestrial digital television standard DVB-T2. IEEE Communications Magazine, 47(10), 146-153. doi:10.1109/mcom.2009.52738222013 ITRS—International Technology Roadmap for Semiconductorshttp://www.itrs2.net/2013-itrs.htmlIbe, E., Taniguchi, H., Yahagi, Y., Shimbo, K., & Toba, T. (2010). Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule. IEEE Transactions on Electron Devices, 57(7), 1527-1538. doi:10.1109/ted.2010.2047907Gil-Tomás, D., Gracia-Morán, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability, 52(11), 2837-2846. doi:10.1016/j.microrel.2012.06.004Neubauer, A., Freudenberger, J., & Khn, V. (2007). Coding Theory. doi:10.1002/9780470519837Morelos-Zaragoza, R. H. (2006). The Art of Error Correcting Coding. doi:10.1002/0470035706Naseer, R., & Draper, J. (2008). DEC ECC design to improve memory reliability in Sub-100nm technologies. 2008 15th IEEE International Conference on Electronics, Circuits and Systems. doi:10.1109/icecs.2008.4674921Saiz-Adalid, L.-J., Gracia-Moran, J., Gil-Tomas, D., Baraza-Calvo, J.-C., & Gil-Vicente, P.-J. (2019). Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. IEEE Access, 7, 151131-151143. doi:10.1109/access.2019.2947315Saiz-Adalid, L.-J., Gil-Vicente, P.-J., Ruiz-GarcĂa, J.-C., Gil-Tomás, D., Baraza, J.-C., & Gracia-Morán, J. (2013). Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. Computer Safety, Reliability, and Security, 178-189. doi:10.1007/978-3-642-40793-2_17Saiz-Adalid, L.-J., Reviriego, P., Gil, P., Pontarelli, S., & Maestro, J. A. (2015). MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10), 2332-2336. doi:10.1109/tvlsi.2014.2357476Gracia-Moran, J., Saiz-Adalid, L. J., Gil-Tomas, D., & Gil-Vicente, P. J. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2132-2142. doi:10.1109/tvlsi.2018.2837220Cadence: Computational Software for Intelligent System Designhttps://www.cadence.comStine, J. E., Castellanos, I., Wood, M., Henson, J., Love, F., Davis, W. R., … Jenkal, R. (2007). FreePDK: An Open-Source Variation-Aware Design Kit. 2007 IEEE International Conference on Microelectronic Systems Education (MSE’07). doi:10.1109/mse.2007.44NanGate FreePDK45 Open Cell Libraryhttp://www.nangate.com/?page_id=232
Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM
[EN] Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction-double error detection (SEC-DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.This research was supported in part by the Spanish Government, project TIN2016-81,075-R, and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032.Baraza Calvo, JC.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2020). Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. Electronics. 9(12):1-30. https://doi.org/10.3390/electronics9122074S130912International Technology Roadmap for Semiconductors (ITRS)http://www.itrs2.net/2013-itrs.htmlJeng, S.-L., Lu, J.-C., & Wang, K. (2007). A Review of Reliability Research on Nanotechnology. IEEE Transactions on Reliability, 56(3), 401-410. doi:10.1109/tr.2007.903188Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K., & Toba, T. (2010). Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule. IEEE Transactions on Electron Devices, 57(7), 1527-1538. doi:10.1109/ted.2010.2047907Boussif, A., Ghazel, M., & Basilio, J. C. (2020). Intermittent fault diagnosability of discrete event systems: an overview of automaton-based approaches. Discrete Event Dynamic Systems, 31(1), 59-102. doi:10.1007/s10626-020-00324-yConstantinescu, C. (2003). Trends and challenges in VLSI circuit reliability. IEEE Micro, 23(4), 14-19. doi:10.1109/mm.2003.1225959Bondavalli, A., Chiaradonna, S., Di Giandomenico, F., & Grandoni, F. (2000). Threshold-based mechanisms to discriminate transient from intermittent faults. IEEE Transactions on Computers, 49(3), 230-245. doi:10.1109/12.841127Contant, O., Lafortune, S., & Teneketzis, D. (2004). Diagnosis of Intermittent Faults. Discrete Event Dynamic Systems, 14(2), 171-202. doi:10.1023/b:disc.0000018570.20941.d2Sorensen, B. A., Kelly, G., Sajecki, A., & Sorensen, P. W. (s. f.). An analyzer for detecting intermittent faults in electronic devices. Proceedings of AUTOTESTCON ’94. doi:10.1109/autest.1994.381590Gracia-Moran, J., Gil-Tomas, D., Saiz-Adalid, L. J., Baraza, J. C., & Gil-Vicente, P. J. (2010). Experimental validation of a fault tolerant microcomputer system against intermittent faults. 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN). doi:10.1109/dsn.2010.5544288Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2), 147-160. doi:10.1002/j.1538-7305.1950.tb00463.xSaiz-Adalid, L.-J., Gil-Vicente, P.-J., Ruiz-GarcĂa, J.-C., Gil-Tomás, D., Baraza, J.-C., & Gracia-Morán, J. (2013). Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. Computer Safety, Reliability, and Security, 178-189. doi:10.1007/978-3-642-40793-2_17Frei, R., McWilliam, R., Derrick, B., Purvis, A., Tiwari, A., & Di Marzo Serugendo, G. (2013). Self-healing and self-repairing technologies. The International Journal of Advanced Manufacturing Technology, 69(5-8), 1033-1061. doi:10.1007/s00170-013-5070-2Maiz, J., Hareland, S., Zhang, K., & Armstrong, P. (s. f.). Characterization of multi-bit soft error events in advanced SRAMs. IEEE International Electron Devices Meeting 2003. doi:10.1109/iedm.2003.1269335Schroeder, B., Pinheiro, E., & Weber, W.-D. (2011). DRAM errors in the wild. Communications of the ACM, 54(2), 100-107. doi:10.1145/1897816.1897844BanaiyanMofrad, A., Ebrahimi, M., Oboril, F., Tahoori, M. B., & Dutt, N. (2015). Protecting caches against multi-bit errors using embedded erasure coding. 2015 20th IEEE European Test Symposium (ETS). doi:10.1109/ets.2015.7138735Kim, J., Sullivan, M., Lym, S., & Erez, M. (2016). All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory. 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). doi:10.1109/isca.2016.60Hwang, A. A., Stefanovici, I. A., & Schroeder, B. (2012). Cosmic rays don’t strike twice. ACM SIGPLAN Notices, 47(4), 111-122. doi:10.1145/2248487.2150989Gil-Tomás, D., Gracia-Morán, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability, 52(11), 2837-2846. doi:10.1016/j.microrel.2012.06.004Plasma CPU Modelhttps://opencores.org/projects/plasmaArlat, J., Aguera, M., Amat, L., Crouzet, Y., Fabre, J.-C., Laprie, J.-C., … Powell, D. (1990). Fault injection for dependability validation: a methodology and some applications. IEEE Transactions on Software Engineering, 16(2), 166-182. doi:10.1109/32.44380Gil-Tomas, D., Gracia-Moran, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection. IEEE Design & Test of Computers, 29(6), 66-73. doi:10.1109/mdt.2011.2179514Rashid, L., Pattabiraman, K., & Gopalakrishnan, S. (2010). Modeling the Propagation of Intermittent Hardware Faults in Programs. 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing. doi:10.1109/prdc.2010.52Amiri, M., Siddiqui, F. M., Kelly, C., Woods, R., Rafferty, K., & Bardak, B. (2016). FPGA-Based Soft-Core Processors for Image Processing Applications. Journal of Signal Processing Systems, 87(1), 139-156. doi:10.1007/s11265-016-1185-7Hailesellasie, M., Hasan, S. R., & Mohamed, O. A. (2019). MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/iscas.2019.8702589Mittal, S. (2018). A survey of FPGA-based accelerators for convolutional neural networks. Neural Computing and Applications, 32(4), 1109-1139. doi:10.1007/s00521-018-3761-1Intel Completes Acquisition of Alterahttps://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/#gs.mi6ujuAMD to Acquire Xilinx, Creating the Industry’s High Performance Computing Leaderhttps://www.amd.com/en/press-releases/2020-10-27-amd-to-acquire-xilinx-creating-the-industry-s-high-performance-computingKim, K. H., & Lawrence, T. F. (s. f.). Adaptive fault tolerance: issues and approaches. [1990] Proceedings. Second IEEE Workshop on Future Trends of Distributed Computing Systems. doi:10.1109/ftdcs.1990.138292Gonzalez, O., Shrikumar, H., Stankovic, J. A., & Ramamritham, K. (s. f.). Adaptive fault tolerance and graceful degradation under dynamic hard real-time scheduling. Proceedings Real-Time Systems Symposium. doi:10.1109/real.1997.641271Jacobs, A., George, A. D., & Cieslewski, G. (2009). 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Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection
(c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.[EN] Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.This work was supported in part by the Spanish Government under Project TIN2016-81075-R, and in part by the Primeros Proyectos de Investigacion, Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), Valencia, Spain, under Project PAID-06-18 20190032.Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2019). Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. IEEE Access. 7:151131-151143. https://doi.org/10.1109/ACCESS.2019.2947315S151131151143
Enhancement of fault injection techniques based on the modification of VHDL code
Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. First, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Second, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper, we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.Baraza Calvo, JC.; Gracia-Morán, J.; Blanc Clavero, S.; Gil Tomás, DA.; Gil Vicente, PJ. (2008). Enhancement of fault injection techniques based on the modification of VHDL code. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16(6):693-706. doi:10.1109/TVLSI.2008.2000254S69370616
Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System
© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment of a fault-tol- erant computer system against intermittent faults. The applied methodology lies in VHDL-based fault injection, which allows the assessment in early design phases, together with a high level of observability and controllability. The evaluated system is a duplex microcontroller system with cold stand-by sparing. A wide set of intermittent fault models have been injected, and from the simulation traces, coverages and latencies have been measured. Markov models for this system have been generated and some dependability functions, such as reliability and safety, have been calculated. From these results, some enhancements of detection and recovery mechanisms have been suggested. The methodology presented is general to any fault-tolerant computer system.This work was supported in part by the Universitat Politecnica de Valencia under the Research Project SP20120806, and in part by the Spanish Government under the Research Project TIN2012-38308-C02-01. Associate Editor: J. Shortle.Gil Tomás, DA.; Gracia Morán, J.; Baraza Calvo, JC.; Saiz Adalid, LJ.; Gil Vicente, PJ. (2016). Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System. IEEE Transactions on Reliability. 65(2):648-661. https://doi.org/10.1109/TR.2015.2484058S64866165
Characterisation of the volatile profile of microalgae and cyanobacteria using solid-phase microextraction followed by gas chromatography coupled to mass spectrometry
[EN] Microalgae and microalgae-derived ingredients are one of the top trends in the food industry. However, consumers' acceptance and purchase intention of a product will be largely affected by odour and flavour. Surprisingly, the scientific literature present a very limited number of studies on the volatile composition of microalgae and cyanobacteria. In order to fill the gap, the main objective of the present study was to elucidate the volatile composition of seven microalgal and cyanobacterial strains from marine and freshwaters, with interest for the food industry while establishing its potential impact in odour. Among the seven selected strains, Arthrospira platensis showed the highest abundance and chemical diversity of volatile organic compounds (VOCs). Aldehydes, ketones, and alcohols were the families with the highest diversity of individual compounds, except in Arthrospira platensis and Scenedesmus almeriensis that showed a profile dominated by branched hydrocarbons. Marine strains presented a higher abundance of sulfur compounds than freshwater strains, while the ketones individual profile seemed to be more related to the taxonomical domain. The results of this study indicate that the VOCs composition is mainly driven by the individual strain although some volatile profile characteristics could be influenced by both environmental and taxonomical factors.This work was conducted in the framework of the SABANA Project funded by the EU H2020 Research and Innovation Programme (Grant agreement 727874), ALGALPROT Project funded by CEI·MAR (CEIJ-002) and financial support provided by the Basque Country Government (IT944-16)
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