Electrical parameters extraction of CMOS floating-gate inverters

This work provides an accurate methodology for extracting the floating-gate gain factory, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays an important role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation

A low-complexity current-mode WTA circuit based on CMOS Quasi-FG inverters

In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy-speed tradeoff when compared to other reported WTA architectures

Fowler-Nordheim tunneling characterization on Poly1-Poly2 capacitors for the implementation of analog memories in CMOS 0.5 m technology

The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5 m technology are presented. This characterization allows the development, design, and characterization of a newcurrent-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture

A CMOS Micro-power, Class-AB Flipped Voltage Follower using the quasi floating-gate technique

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the Flipped Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain-bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz

Stable Matching of Users in a Ridesharing Model

A ridesharing system is a transport mode where two or more users share the same vehicle and divide the trip’s expenses based on similar routes and itineraries. Popular ridesharing systems, such as Uber, Flinc, and Lyft, define a matching among users based only on the coincidence of routes. However, these systems do not guarantee a stable matching (i.e., a matching in which no user prefers another different from the assigned one). In this work, a new ridesharing system model is proposed, including three types of trips: identical, inclusive, and partial. This model is used to introduce a new algorithm to address the stable matching problem for ridesharing systems. Finally, a set of experimental simulations of the proposed algorithm is conducted. Experimental results show that the proposed algorithm always produces a stable matching