A Generalized Predictive Controlled T-type power inverter with a deterministic dc-link capacitor voltage balancing approach

The thesis consists of implementing a Generalized Predictive Control (GPC) strategy for controlling the output voltage of the T-type converter with output LC filter, whose control signals are modulated by a fast three-dimensional Space Vector Modulation (SVM). The GPC strategy used for the T-type converter involves developing a system of dynamic equations from the output LC filter and load, which is transformed to a Controlled Auto-Regressive and Moving-Average (CARIMA) model in order to obtain a sequence of control signals, so that a cost function is optimized and the reference is tracked. The core of the thesis addresses the main problem of dc-link capacitor balancing. This is done by modeling the converter and deploying a mathematical analysis of the capacitor voltage difference dynamics, by singular perturbation approach. This analysis results in an explicit sinusoidal disturbance. Now, classical control theory is applied by using a Luenberger Observer (LO) in order to estimate the disturbance and encounter it, thereby keeping the dc-link capacitor voltage balanced in the due flow of the modulation and output voltage control. By this method, the output voltage across the filter capacitor is controlled, the dc-link capacitor voltage is balanced and the lowfrequency voltage ripples present in the dc-link of the T-type converter are reduced to an acceptable level.Máster en Electrónica, Tratamiento de Señal y Comunicacione

Experimental demonstration of in-memory computing in a ferrofluid system

Magnetic fluids are excellent candidates for several important research fields including energy harvesting, biomedical applications, soft robotics, and exploration. However, notwithstanding relevant advancements such as shape reconfigurability, that have been demonstrated, there is no evidence for their computing capability, including the emulation of synaptic functions, which requires complex non-linear dynamics. Here, it is experimentally demonstrated that a Fe3O4 water-based ferrofluid (FF) can perform electrical analogue computing and be programmed using quasi direct current (DC) signals and read at radio frequency (RF) mode. Features have been observed in all respects attributable to a memristive behavior, featuring both short and long-term information storage capacity and plasticity. The colloid is capable of classifying digits of a 8×8 pixel dataset using a custom in-memory signal processing scheme, and through physical reservoir computing by training a readout layer. These findings demonstrate the feasibility of in-memory computing using an amorphous FF system in a liquid aggregation state. This work poses the basis for the exploitation of a FF colloid as both an in-memory computing device and as a full-electric liquid computer thanks to its fluidity and the reported complex dynamics, via probing read-out and programmingports

Memristor Based Event Driven Neuromorphic Nano-CMOS Processor

‘Neuromorphic engineering’ has been showing significant developments in recent days. The word ‘neuromorphic’ was first coined by Caver Mead, which is morphing biological brain on-chip [1]. The main idea is to use the sub-threshold currents of transistors and mimic the biophysical properties that the neurons have. These brain-inspired neuromorphic computing systems have attracted research interest since they are alternate to classical von Neumann [2], computer architectures mainly because of the co-existence of memory and processing units. The renowned neuromorphic chips in the last few decades are Neurogrid [3], Truenorth [4], BrainScaleS [5], and SpiNNaker [6]. Memristors are the fourth fundamental passive-bipolar device, that links charge and flux non-linearly. When Chua coined the word ‘Memristor’ in the late 70s, there was no hint of the existence of the device [7]. Later when the physical existence of the device was shown by HP Labs, it sparked a new wave of enthusiasm among the neuromorphic community [8]. Properties such as non-volatile storage, nano-size existence, non-abrupt switching transition, continuously distributed resistance states, and repeatable behavior convinced the neuromorphic researcher to realize memristors as favorable synaptic elements for neuromorphic systems. In this scenario, the research activities carried out in this doctoral dissertation demonstrates a neuromorphic processing chip for event-driven learning, using memristors as synapses, which are integrated monolithically above the CMOS layers. Although memristors emerged as a potential synapse to solve the density challenge, scalability remains an important bottleneck. Neuromorphic systems should be made more scalable to realize large networks. To contribute to this, we focus on significant challenges in memristor-based neuromorphic hardware. They are- 1) Implementing an on-chip three-stage bulk-based calibration scheme for memristive crossbars and using its low-power inference for recognizing patterns using template matching, programming, and learning. 2) Designing a new current attenuator that is used for efficient crossbar read-outs with a scale-down factor of about 104. The thesis also demonstrates- characterization of three different memristors on various test-benches such as- ArC One Instrument, a full-custom test-PCB, and using probe station with semiconductor parameter analyzer

A Current Attenuator for Efficient Memristive Crossbars Read-Out

This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.European Union's Horizon 2020 No 687299 NeuRAMEuropean Union's Horizon 2020 No 824164 HERME

Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration

Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability and low power operation. After learning, however, a read inference can be made low-power by applying very small amplitude read pulses, which require much smaller driving currents per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately, applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome this, we propose nely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4 4 proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a 4 4 1T1R synapse crossbarwas designed and fabricated in the CEA-LETI MAD200 technology, which uses monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the post-synaptic circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization, template matching, and pattern recognition using STDP learning, and to demonstrate the use of on-chip offset-calibrated low-power ampli ers. According to our experiments, the minimum possible inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some suggestions for future work in this direction.International Consortium of Nanotechnologies (ICON) Grant G0086European Union H2020 grant 824164 (HERMES)European Union H2020 grant 871371 (MeM-Scales)European Union H2020 grant 871501 (NeurONN)European Union H2020 grant 899559 (SpinAge)European Union H2020 grant PCI2019-111826-2 (APPROVIS3D)Spanish Ministry of Science and Innovation Grant PID2019-105556GB-C31 (NANOMIND)Spanish Ministry of Science and Innovation / FEDER Grant PID2019-103876RB-I00 (CORDION)Junta de Andalucía (Spain) Grant US-1260118 (Neuro-Radio)Universidad de Sevilla ( Spain) VI PPI

Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages- coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.EU H2020 grant 687299 NeuRAM3EU H2020 grant 824164 HERMESEU H2020 grant 871501 NeurONNEU H2020 grant 871371 MeM-ScalesSpanish Ministry of Economy and Competitiveness TEC2015-63884-C2-1-P (COGNET)Spanish Ministry of Economy and Competitiveness G0086 ICONUniversidad de Sevilla (España) VI PPI