Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures

International audienceA small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures implemented in 32 nm CMOS technology. The DFLL control is designed so that the closed-loop system is able to cope with process variability while it rejects temperature changes and supply voltage slow variations. Therefore the DFLL is made of three main blocks, namely a Digitally Controlled Oscillator (DCO), a "sensor" that measures the frequency of the signal at the output of the DCO and a controller. A strong emphasis is set on the loop filter architecture choice and the tuning of its parameters. An analytical model of the DCO is deduced from accurate Spice simulations. The delay introduced by the sensor is also taken into account to design. From these models, an optimal and robust controller with a minimum implementation area is developed. Here, "optimal" means that the controller is computed via the minimization of a given criterion while the "robustness" capability ensures that the closed-loop system is tolerant to process and temperature variations in a given range. Therefore, performances of the closed-loop system are ensured whatever the system characteristics are in a given range

Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems

International audienceThe explosion of IoT and wearable devices determined a rising attention towards energy harvesting as source for powering these systems. In this context, many applications cannot afford the presence of a battery because of size, weight and cost issues. Therefore, due to the intermittent nature of ambient energy sources, these systems must be able to save and restore their state, in order to guarantee progress across power interruptions. In this work, we propose a specialized backup/restore controller that dynamically tracks the memory accesses during the execution of the program. The controller then commits the changes to a snapshot in a Non-Volatile Memory (NVM) when a power failure is detected. Our approach does not require complex hybrid memories and can be implemented with standard components. Results on a set of benchmarks show an average 8× reduction in backup size. Thanks to our dedicated controller, the backup time is further reduced by more than 100×, with an area and power overhead of only 0.4% and 0.8%, respectively, w.r.t. a low-end IoT node

Adaptive Stackable 3D Cache Architecture for Manycores

International audienceWith the emergence of manycore architectures, the need of on-chip memories such as caches grows faster than the number of cores. Moreover the bandwidth to off-chip memories is saturating. Big memory caches can alleviate the pressure to off-chip accesses. In this paper, we present an adaptive 3D cache architecture taking advantage of dense vertical connections in stacked chips. Then we propose a dynamically adaptive mechanism to optimize the use of the aforementioned 3D cache architecture according to the workload needs. Finally, we analyze the gain on memory accesses and on software execution time in a realistic model of manycore architecture and we study the hardware cost of our proposal, showing that our approach can lead to a 50% reduction of both external memory accesses and application execution time

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

International audienceNetworks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

International audienceThis paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization

International audienceAchieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its V$_{min}$ has been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation

Towards Low-Power Embedded ECoG Decoding

International audienceThe ability to read intents from the brain is no longer science fiction. This requires acquiring and decoding the brain signals to make them usable in different applications. The signal processing requires high computational capacities and consequently high energy consumption. This paper introduces the flows for brain signal decoding and focuses on electrocorticography (ECoG) approaches for motor imagery. SoA ECoG decoding algorithms require significant computing power creating a need for specialized low-power circuits for embedded use

Towards Low-Power Embedded ECoG Decoding

International audienceThe ability to read intents from the brain is no longer science fiction. This requires acquiring and decoding the brain signals to make them usable in different applications. The signal processing requires high computational capacities and consequently high energy consumption. This paper introduces the flows for brain signal decoding and focuses on electrocorticography (ECoG) approaches for motor imagery. SoA ECoG decoding algorithms require significant computing power creating a need for specialized low-power circuits for embedded use

LDO-assisted Voltage Selector over 0.5-to-1V VDD range for fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

International audienceThis paper presents a 95% power-efficient duty-cycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2mm 2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load ([email protected] 2). This therefore allows a MHz dynamic voltage scaling rate