Vertically Integrated Nanowire-Based Unified Memory

A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications

Gate Capacitance Coupling of Double-Gate Carbon Nanotube Network Transistors

Carbon nanotube (CNT) network channels constructed using a high-purity CNT solution for use in CNT thin-film transistors have the advantages of the possibility of requiring a low-temperature process and needing no special equipment. However, there are empty spaces between individual CNTs, resulting in unexpected effects. In this study, double-gate (DG) CNT network transistors were fabricated and measured in four different configurations to observe the capacitive coupling effects between the top gate (TG) and bottom gate (BG) in the DG structure. As a result, the electrical characteristics measured with the BG with a thicker gate oxide while floating the TG were similar to those measured with the TG with a thinner gate oxide. A comparison of the measured transfer curves showed that TG and BG were strongly coupled through the empty spaces in the channels. In addition, we evaluated the capacitance coupling effect due to changes in the CNT density, which is closely related to the empty space of the network channel. Finally, we proposed a method to determine the effective gate capacitance by considering the empty spaces between CNTs, which enabled the accurate evaluation of mobility. The effects of these materials were demonstrated by fabricating transistors using Al2O3, HfO2, and ZrO2 as TG oxide materials. By focusing on considerations based on the properties of CNT materials, our study provides valuable insights into accurate electrical modeling and potential advancements in CNT-based devices

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction

Cytocompatibility of Ti₃AlC₂, Ti₃SiC₂, and Ti₂AlN: <i>In Vitro</i> Tests and First-Principles Calculations

Herein, the cytocompatibility of selected MAX phases, Ti₃AlC₂, Ti₃SiC₂, and Ti₂AlN, were systematically evaluated using <i>in vitro</i> tests for the first time. These phases were anoxic to preosteoblasts and fibroblasts. Compared with the strong viable fibroblasts, the different cellular responses of these materials were clearly distinguishable for the preosteoblasts. Under an osteoblastic environment, Ti₂AlN exhibited better cell proliferation and differentiation performance than Ti₃AlC₂ and Ti₃SiC₂. Moreover, the performance was superior to that of a commercial Ti–6Al–4V alloy and comparable to that of pure Ti. A possible mechanism was suggested based on the different surface oxidation products, which were determined from the binding energy of adsorbed Ca²⁺ ions using first-principles calculations. Compared with the partially oxidized TiC_<i>x</i>O_<i>y</i> layer on Ti₃AlC₂ and Ti₃SiC₂, the partially oxidized TiN_<i>x</i>O_<i>y</i> layer on the Ti₂AlN had a stronger affinity to the Ca²⁺ ions, which indicated the good cytocompatibility of Ti₂AlN

Vertically Integrated Multiple Nanowire Field Effect Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling

Three-Dimensional Printed Poly(vinyl alcohol) Substrate with Controlled On-Demand Degradation for Transient Electronics

Electronics that degrade after stable operation for a desired operating time, called transient electronics, are of great interest in many fields, including biomedical implants, secure memory devices, and environmental sensors. Thus, the development of transient materials is critical for the advancement of transient electronics and their applications. However, previous reports have mostly relied on achieving transience in aqueous solutions, where the transience time is largely predetermined based on the materials initially selected at the beginning of the fabrication. Therefore, accurate control of the transience time is difficult, thereby limiting their application. In this work, we demonstrate transient electronics based on a water-soluble poly­(vinyl alcohol) (PVA) substrate on which carbon nanotube (CNT)-based field-effect transistors were fabricated. We regulated the structural parameters of the PVA substrate using a three-dimensional (3D) printer to accurately control and program the transience time of the PVA substrate in water. The 3D printing technology can produce complex objects directly, thus enabling the efficient fabrication of a transient substrate with a prescribed and controlled transience time. In addition, the 3D printer was used to develop a facile method for the selective and partial destruction of electronics

Three-Dimensionally Printed Micro-electromechanical Switches

Three-dimensional (3D) printers have attracted considerable attention from both industry and academia and especially in recent years because of their ability to overcome the limitations of two-dimensional (2D) processes and to enable large-scale facile integration techniques. With 3D printing technologies, complex structures can be created using only a computer-aided design file as a reference; consequently, complex shapes can be manufactured in a single step with little dependence on manufacturer technologies. In this work, we provide a first demonstration of the facile and time-saving 3D printing of two-terminal micro-electromechanical (MEM) switches. Two widely used thermoplastic materials were used to form 3D-printed MEM switches; freely suspended and fixed electrodes were printed from conductive polylactic acid, and a water-soluble sacrificial layer for air-gap formation was printed from poly­(vinyl alcohol). Our 3D-printed MEM switches exhibit excellent electromechanical properties, with abrupt switching characteristics and an excellent on/off current ratio value exceeding 10⁶. Therefore, we believe that our study makes an innovative contribution with implications for the development of a broader range of 3D printer applications (e.g., the manufacturing of various MEM devices and sensors), and the work highlights a uniquely attractive path toward the realization of 3D-printed electronics

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (<i>V</i>_TH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs