52 km-long transmission link using a 50 Gb/s O-band silicon microring modulator co-packaged with a 1V-CMOS driver

We present an O-band silicon microring modulator with up to 50 Gb/s modulation rates, co-packaged with a 1V-CMOS driver in a dispersion un-compensated, transmission experiment through 52 km of standard single-mode fiber. The experimental results show 10(-9) error-rate operation with a negligible power penalty of 0.2 dB for 40 Gb/s and wide-open eye diagrams for 50 Gb/s data, corresponding to a record high bandwidth-distance product of 2600 Gb.km/s. A comparative analysis between the proposed transmitter assembly and a commercial LiNbO3 modulator revealed a moderate increase of 3.8 dB in power penalty, requiring only 20% of the driving voltage level used by the commercial modulator

High-performance end-to-end deep learning IM/DD link using optics-informed neural networks

: In this paper, we introduce optics-informed Neural Networks and demonstrate experimentally how they can improve performance of End-to-End deep learning models for IM/DD optical transmission links. Optics-informed or optics-inspired NNs are defined as the type of DL models that rely on linear and/or nonlinear building blocks whose mathematical description stems directly from the respective response of photonic devices, drawing their mathematical framework from neuromorphic photonic hardware developments and properly adapting their DL training algorithms. We investigate the application of an optics-inspired activation function that can be obtained by a semiconductor-based nonlinear optical module and is a variant of the logistic sigmoid, referred to as the Photonic Sigmoid, in End-to-End Deep Learning configurations for fiber communication links. Compared to state-of-the-art ReLU-based configurations used in End-to-End DL fiber link demonstrations, optics-informed models based on the Photonic Sigmoid show improved noise- and chromatic dispersion compensation properties in fiber-optic IM/DD links. An extensive simulation and experimental analysis revealed significant performance benefits for the Photonic Sigmoid NNs that can reach below BER HD FEC limit for fiber lengths up to 42 km, at an effective bit transmission rate of 48 Gb/s

4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4 x 50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of -9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

Chip-to-chip interconnect for 8-socket direct connectivity using 25Gb/s O-band integrated transceiver and routing circuits

We present an O-band Chip-to-Chip Interconnect for 8-socket direct connectivity exploiting a Si-based Ring Modulator and a packaged PD-TIA connected over a Si-based 8×8 AWGR routing module. Eight routing scenarios are experimentally demonstrated at 25Gb/s revealing error-free operation

A 40 Gb/s chip-to-chip interconnect for 8-socket direct connectivity using integrated photonics

We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals

400 Gb/s silicon photonic transmitter and routing WDM technologies for glueless 8-socket chip-to-chip interconnects

Arrayed Waveguide Grating Router (AWGR)-based interconnections for Multi-Socket Server Boards (MSBs) have been identified as a promising solution to replace the electrical interconnects in glueless MSBs towards boosting processing performance. In this article, we present an 8-socket glueless optical flat-topology Wavelength Division Multiplexing (WDM)-based point-to-point (P2P) interconnect pursued within the H2020 ICT project ICT-STREAMS and we report on our latest achievements in the deployment of the constituent silicon (Si)-photonic transmitter and routing building blocks, exploiting experimentally obtained performance metrics for analyzing the 8-socket chip-to-chip (C2C) connectivity in terms of throughput and energy efficiency. We demonstrate an 8-channel WDM Si-photonic microring-based transmitter (Tx) capable of providing 400 (8 x 50) Gb/s non-return-to-zero (NRZ) Tx capacity and an 8 x 8 Coarse-WDM (CWDM) Si-AWGR with verified cyclic data routing capability in O-band. Following an overview of our recently demonstrated crosstalk (XT)-aware wavelength allocation scheme, that enables fully-loaded AWGR-based interconnects even for typical sub-optimal XT values of silicon integrated CWDM AWGRs, we validate the performance of a full-scale 8-socket interconnect architecture through physical layer simulations exploiting experimentally-verified simulation models for the underlying Si-photonic Tx and routing circuits. This analysis reveals a total aggregate capacity of 1.4 Tb/s for an 8-socket interconnect when operating with 25 Gb/s line-rates, which can scale to 2.8 Tb/s at an energy efficiency of just 5.02 pJ/bit by exploiting the experimentally verified building block performance at 50 Gb/s line. This highlights the perspectives for up to 69% energy savings compared to the standard QuickPath Interconnect (QPI) typically employed in electronic glueless MSB interconnects, while scaling the single-hop flat connectivity from 4- to 8-socket interconnection systems

Silicon circuits for chip-to-chip communications in multi-socket server board interconnects

Multi-socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with the interconnect technology comprising a key element in boosting processing performance. Here, we present an overview of the current electrical interconnects for MSBs, outlining the main challenges currently faced. We propose the use of silicon photonics (SiPho) towards advancing interconnect throughput, socket connectivity and energy efficiency in MSB layouts, enabling a flat-topology wavelength division multiplexing (WDM)-based point-to-point (p2p) optical MSB interconnect scheme. We demonstrate WDM SiPho transceivers (TxRxs) co-assembled with their electronic circuits for up to 50 Gb/s line rate and 400 Gb/s aggregate data transmission and SiPho arrayed waveguide grating routers that can offer collision-less time of flight connectivity for up to 16 nodes. The capacity can scale to 2.8 Gb/s for an eight-socket MSB, when line rate scales to 50 Gb/s, yielding up to 69% energy reduction compared with the QuickPath Interconnect and highlighting the feasibility of single-hop p2p interconnects in MSB systems with >4 sockets

Ολοκληρωμένα κυκλώματα φωτονικής πυριτίου και οπτικοί μεταγωγείς υψηλής χωρητικότητας για διασύνδεση σε κέντρα δεδομένων

The explosive growth of Data Center (DC) traffic is putting strenuous requirements in DC operators, that must push the performance envelope of the underlying network infrastructure towards (i) high network and resource utilization (ii) high bandwidth (iii) low latency and (iv) high energy efficiency. In this context, optical interconnects arise as a promising technological candidate for future DC and High-Performance Computing (HPC) environments, aiming to replace electronic interconnects with high-bandwidth, low-power optical solutions across the DC and HPC network hierarchy. The main research contributions of this thesis revolved around the development of an Optical Packet Switch (OPS) architecture, towards addressing the problem of high-port, high-bandwidth, low-latency switching as well as the study and deployment of Silicon Photonics (SiPho) circuits, outlining a roadmap towards next generation optical switches and transceivers. At first, in view of meeting the networking requirements in terms of port count and latency of disaggregated DC architectures, an optical switch named Hipoλaos (High Port λ-routed All Optical Switch) was proposed and demonstrated. Hipoλaos can efficiently integrate Spanke-based switching with Arrayed Waveguide Grating Router (AWGR)-based wavelength routing and optical feedforward buffering, towards providing high-port layouts with sub-μs latency. A functional 1024-port plane of the Hipoλaos switch was constructed and experimentally demonstrated, using 10 Gb/s unicast and multicast packets, revealing error-free operation for all cases. Moving however towards practical optical switch implementations, requires an integration approach, with the um-SOI platform standing out as a promising integration vehicle for the Hipoλaos architecture. To this end, the basic building block of optical feed forward buffering i.e. a Time Slot Interchanger (TSI), was proposed and experimentally validated for 10 Gb/s data packets, with the optical delay lines realized through um-SOI waveguides. Followingly, an integrated version of the Hipoλaos switch was proposed, relying on um-SOI circuitry for both buffering and wavelength routing. The prototype 9×9 switch employed um-SOI delay lines for buffering and a 3×3 Echelle Grating for routing and was experimentally evaluated using 10 Gb/s packets for both unicast and multicast modes, revealing error-free operation for all cases. Consequently, towards addressing the need of a low-cost, direct detection scheme, for interconnecting geographically distributed DCs, a 50 Gb/s SiPho O-band Ring Modulator (RM)-based optical transmitter co-packaged with a high-speed driver was proposed and presented. The transmitter achieved a record high bandwidth distance product of 2600 Gb-kms (50 Gb/s × 52 km) , featuring an Extinction Ratio (ER) of 4.15 dB and a power consumption of 40 mW. Finally, a 200 Gb/s and a 400 Gb/s SiPho optical transceiver (TxRx) were proposed and demonstrated, with the developed modules leveraging Wavelength Division Multiplexing (WDM) and the significant advantages of RM-based transmitters, in terms of footprint and energy consumption versus approaches based on Mach Zehnder Modulators (MZM). The 200 Gb/s module featured four 50 Gb/s channels, was co-packaged with SiGe drivers and transimpedance amplifiers (TIA) and exhibited a 4 pJ/bit energy efficiency. The scaled up 400 Gb/s TxRx version featured 8 channels with a channel spacing of 1.14 nm and achieved an average ER of 4.5 dB.Η εκρηκτική αύξηση της πληροφορίας που διακινείται μέσω των Κέντρων Δεδομένων (ΚΔ) δημιουργεί μια σειρά από αυστηρές προδιαγραφές στους διαχειριστές τους, που πρέπει να αυξήσουν τις δυνατότητες των υπάρχων δικτύων προσφέροντας : (i) υψηλή αξιοποίηση του δικτύου και των διαθέσιμων πόρων (ii) υψηλό ρυθμό μετάδοσης (iii) χαμηλή καθυστέρηση και (iv) χαμηλή κατανάλωση. Σε αυτό το πλαίσιο, οι τεχνολογίες οπτικής διασύνδεσης εμφανίζονται σαν μια τεχνολογική πλατφόρμα, που μπορεί να αντικαταστήσει τις τωρινές ηλεκτρονικές διασυνδέσεις με υψηλού ρυθμού, χαμηλής κατανάλωσης οπτικές υλοποιήσεις σε διάφορα τμήματα του δικτύου. Η έρευνα που έχει πραγματοποιηθεί στο πλαίσιο της παρούσης διατριβής έχει επικεντρωθεί στην ανάπτυξη ενός οπτικού μεταγωγέα πακέτου υψηλού ρυθμού, χαμηλής καθυστέρησης και υψηλού αριθμού θυρών, καθώς και στην μελέτη και υλοποίηση φωτονικών ολοκληρωμένων κυκλωμάτων, για τη νέα γενιά οπτικών μεταγωγέων και αναμεταδοτών. Στην αρχή της παρούσας διατριβής, παίρνοντας υπόψη τις προδιαγραφές που επιβάλλονται από τις τεχνικές διαχωρισμού πόρων στα δίκτυα ΚΔ, προτάθηκε και παρουσιάστηκε μια αρχιτεκτονική οπτικού μεταγωγέα πακέτου, που ονομάζεται Hipoλaos (High port λ-routed all optical switch). Ο μεταγωγέας Hipoλaos υλοποιεί ένα υβριδικό σχήμα μεταγωγής, ακολουθώντας την Spanke αρχιτεκτονική, αλλά και ενσωματώνει τις δυνατότητες δρομολόγησης σημάτων μέσω συστοιχιών κυματοδηγών περίθλασης (AWGR) και προσωρινής αποθήκευσης στο οπτικό πεδίο, για να προσφέρει υψηλό αριθμό θυρών και καθυστέρηση μικρότερη του μs. Στα πλαίσια της διατριβής, υλοποιήθηκε πειραματικά ένα επίπεδο 1024-θυρών αρχιτεκτονικής Hipoλaos, και επιβεβαιώθηκε η λειτουργικότητα του για πακέτα 10 Gb/s. Στη συνέχεια, μελετήθηκε η δυνατότητα μεταφοράς του μεταγωγέα στη πλατφόρμα φωτονικής ολοκλήρωσης πυριτίου-επί-οξιδίου διαστάσεων μικρό μετρου (μm-SOI). Με αυτό το σκοπό, σχεδιάστηκε το βασικό δομικό στοιχείο της προσωρινής οπτικής αποθήκευσης πακέτου, δηλαδή ένα οπτικός ενναλάκτης χρονοθυρίδας (TSI), με τις οπτικές καθυστερήσεις υλοποιημένες μέσω κυματοδηγών τεχνολογίας um-SOI. Στη συνέχεια, σχεδιάστηκε ένας μεταγωγέας Hipoλaos, με την προσωρινή αποθήκευση, μέσω γραμμών καθυστέρησης, και τη δρομολόγηση μήκους κύματος, μέσω ενός 3×3 φράγματος περίθλασης Echelle, να βασίζονται σε um-SOI στοιχεία. Η λειτουργία του πρότυπου 9×9 οπτικού μεταγωγέα επιβεβαιώθηκε πειραματικά για πακέτα 10 Gb/s, για απλή λειτουργία και για λειτουργία πολύ-εκπομπής ,παρουσιάζοντας ρυθμό σφαλμάτων 1E-9

Silicon Photonics towards Disaggregation of Resources in Data Centers

In this paper, we demonstrate two subsystems based on Silicon Photonics, towards meeting the network requirements imposed by disaggregation of resources in Data Centers. The first one utilizes a 4 × 4 Silicon photonics switching matrix, employing Mach Zehnder Interferometers (MZIs) with Electro-Optical phase shifters, directly controlled by a high speed Field Programmable Gate Array (FPGA) board for the successful implementation of a Bloom-Filter (BF)-label forwarding scheme. The FPGA is responsible for extracting the BF-label from the incoming optical packets, carrying out the BF-based forwarding function, determining the appropriate switching state and generating the corresponding control signals towards conveying incoming packets to the desired output port of the matrix. The BF-label based packet forwarding scheme allows rapid reconfiguration of the optical switch, while at the same time reduces the memory requirements of the node’s lookup table. Successful operation for 10 Gb/s data packets is reported for a 1 × 4 routing layout. The second subsystem utilizes three integrated spiral waveguides, with record-high 2.6 ns/mm2, delay versus footprint efficiency, along with two Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) wavelength converters, to construct a variable optical buffer and a Time Slot Interchange module. Error-free on-chip variable delay buffering from 6.5 ns up to 17.2 ns and successful timeslot interchanging for 10 Gb/s optical packets are presented