9,133 research outputs found

    A generalized memory test algorithm

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    A general algorithm for testing digital computer memory is presented. The test checks that (1) every bit can be cleared and set in each memory work, and (2) bits are not erroneously cleared and/or set elsewhere in memory at the same time. The algorithm can be applied to any size memory block and any size memory word. It is concise and efficient, requiring the very few cycles through memory. For example, a test of 16-bit-word-size memory requries only 384 cycles through memory. Approximately 15 seconds were required to test a 32K block of such memory, using a microcomputer having a cycle time of 133 nanoseconds

    Application of integration algorithms in a parallel processing environment for the simulation of jet engines

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    The application of Predictor corrector integration algorithms developed for the digital parallel processing environment are investigated. The algorithms are implemented and evaluated through the use of a software simulator which provides an approximate representation of the parallel processing hardware. Test cases which focus on the use of the algorithms are presented and a specific application using a linear model of a turbofan engine is considered. Results are presented showing the effects of integration step size and the number of processors on simulation accuracy. Real time performance, interprocessor communication, and algorithm startup are also discussed

    Performance of a J85-13 compressor with clean and distorted inlet flow

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    The results presented are of a series of experimental tests in which a J85-13 turbojet engine was subjected to both distorted and undistorted inlet total pressure conditions. A distinctive feature of the data base obtained is that it includes compressor interstage information not previously recorded for a J85-13 engine. Each of the eight compressor stages was instrumented to obtain the characteristics of the individual stages for undistorted inlet conditions, and these data are documented in the report along with the undistorted compressor overall performance. Also included in the report is the overall performance of the compressor exposed to 14 different distorted-inlet conditions - 10 circumferential patterns and 4 radial patterns. The distortion patterns were introduced using screens that spoiled from 8 to 50 percent of the compressor face area; the distortion screen density, or the area blocked by the screen wire per unit area of screen, varied from 26 to 69 percent

    Design of a high-speed digital processing element for parallel simulation

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    A prototype of a custom designed computer to be used as a processing element in a multiprocessor based jet engine simulator is described. The purpose of the custom design was to give the computer the speed and versatility required to simulate a jet engine in real time. Real time simulations are needed for closed loop testing of digital electronic engine controls. The prototype computer has a microcycle time of 133 nanoseconds. This speed was achieved by: prefetching the next instruction while the current one is executing, transporting data using high speed data busses, and using state of the art components such as a very large scale integration (VLSI) multiplier. Included are discussions of processing element requirements, design philosophy, the architecture of the custom designed processing element, the comprehensive instruction set, the diagnostic support software, and the development status of the custom design

    An automated procedure for calculating system matrices from perturbation data generated by an EAI Pacer and 100 hybrid computer system

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    Techniques are presented for determining the elements of the A, B, C, and D state variable matrices for systems simulated on an EAI Pacer 100 hybrid computer. An automated procedure systematically generates disturbance data necessary to linearize the simulation model and stores these data on a floppy disk. A separate digital program verifies this data, calculates the elements of the system matrices, and prints these matrices appropriately labeled. The partial derivatives forming the elements of the state variable matrices are approximated by finite difference calculations

    Simulating a small turboshaft engine in real-time multiprocessor simulator (RTMPS) environment

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    A Real-Time Multiprocessor Simulator (RTMPS) has been developed at NASA Lewis Research Center. The RTMPS uses parallel microprocessors to achieve computing speeds needed for real-time engine simulation. This report describes the use of the RTMPS system to simulate a small turboshaft engine. The process of programming the engine equations and distributing them over one, two, and four processors is discussed. Steady-state and transient results from the RTMPS simulation are compared with results from a main-frame-based simulation. Processor execution times and the associated execution time savings for the two and four processor cases are presented using actual data obtained from the RTMPS system. Included is a discussion of why the minimum achievable calculation time for the turboshaft engine model was attained using four processors. Finally, future enhancements to the RTMPS system are discussed including the development of a generalized partitioning algorithm to automatically distribute the system equations among the processors in optimum fashion

    Partitioning and packing mathematical simulation models for calculation on parallel computers

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    The development of multiprocessor simulations from a serial set of ordinary differential equations describing a physical system is described. Degrees of parallelism (i.e., coupling between the equations) and their impact on parallel processing are discussed. The problem of identifying computational parallelism within sets of closely coupled equations that require the exchange of current values of variables is described. A technique is presented for identifying this parallelism and for partitioning the equations for parallel solution on a multiprocessor. An algorithm which packs the equations into a minimum number of processors is also described. The results of the packing algorithm when applied to a turbojet engine model are presented in terms of processor utilization

    “Respectably Dull”: Striptease, Tourism and Reform in Postwar New Orleans

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    The French Quarter of New Orleans and its famous Bourbon Street receive millions of visitors each year and are the subjects of both scholarly study and the popular imagination. Bourbon Street’s history of striptease has largely been untouched by scholars. In the post-World War II period, nightclubs featuring striptease entertainment drew the attention of reform-minded city and police officials, who attempted to purge striptease from the city’s historic district in an effort to whitewash the city’s main tourist area and appeal to potential outside economic industrial opportunities. Through news articles, correspondence, tourism brochures, and published reports, this thesis explores how striptease endured on Bourbon Street despite various reform campaigns against it and shows that striptease was an integral part of the New Orleans tourist economy in the postwar period

    Syntactic awareness and reading development: A training study with young children

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    A number of previous research studies have examined the relationship between syntactic awareness and reading, but few training studies have been reported. In the present study, a 1 a-week training study employing an experimental design, was conducted with 34 Year 1 and 38 Year 2 children to determine whether training in syntactic awareness increased levels of syntactic awareness and reading performance. Prior to the commencement of training, all children were pretested in syntactic awareness as measured by an oral correction task, and in reading. On the basis of these tests, matched pairs of subjects were assigned to experimental and control groups at each Year level. At the conclusion of the training period all subjects were posttested in alternate forms of the same tests used at pretest. The results showed that there were no significant differences between the experimental and control groups, of either grade, at posttest, in syntactic awareness and reading performance. A significant main effect for grade was recorded in the syntactic awareness task, with the Year 2 children performing at a higher /eve/than the Year 1 children. When pretest and posttest scores in syntactic awareness and reading performance were compared, all children, whether they received training or not, improved significantly in their levels of syntactic awareness and also their levels of reading performance. It is suggested that the Improvement in syntactic awareness across all groups may have reflected the influence of the particular curriculum documents used in Western Australian schools. It is further suggested that more training studies are needed to examine the effects which different language curricula may have on the development of syntactic awareness in early readers
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