The Role of Frequency and Duty Cycle on the Gate Reliability of p-GaN HEMTs

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers

Impact of structural and process variations on the time-dependent OFF-state breakdown of p-GaN power HEMTs

In this article, we present an extensive investigation of the time-dependent drain breakdown occurring in GaN-on-Si power HEMTs with p-GaN gate under long-term OFF-state stress. In particular, the time-dependent breakdown induced by high-temperature-reverse-bias stress is investigated as a function of different process and structural variations. Main results demonstrate that, by varying the gate-to-drain distance (L-GD) and the field plates configuration, the physical location of failure changes as well. If L-GD is relatively short (3 mu m), the time-dependent breakdown occurs through the GaN channel layer between drain and source. In this case, a thinner GaN layer significantly improves the device robustness to long-term OFF-state stress. If L-GD is relatively long (>= 4 mu m), the failure occurs between the two-dimensional electron gas (2DEG) and the source field plates. In this second case, the GaN layer thickness and L-GD have no significant impact on the time-dependent breakdown, whereas the field plate lengths can be optimized to reduce the area exposed to high electric fields, hence limiting the probability of failure. Finally, the role of the AlGaN barrier layer has been analyzed as well. If L-GD = 3 mu m, a thinner AlGaN layer is preferred, whereas if L-GD >= 4 mu m, a thicker layer with lower aluminum content gives rise to longer time to breakdown under OFF-State stress

High-Temperature Time-Dependent Gate Breakdown of p-GaN HEMTs

In this article, we present an in-depth high-temperature analysis of the long-term gate reliability in GaN-based power high-electron-mobility transistors (HEMTs) with p-type gate. Three different isolation process options, aimed at improving the time-dependent gate breakdown (TDGB), are proposed and compared by means of constant voltage stress tests performed at different forward gate biases, temperatures, and geometries. In particular, depending on the gate bias and temperature, the breakdown event may occur along the active gate area or through the isolation region. The results show different voltage dependency for such two different failure locations; therefore, two field-acceleration fitting models are needed for the estimation of lifetime. Furthermore, the gate time-to-failure (TTF) shows a non-monotonous temperature dependency at given gate bias. More specifically, a positive and a negative T-derivatives are observed at relatively low and high temperatures, respectively, which are related to active gate area and isolation region failure, respectively

Gate Reliability of p-GaN Power HEMTs Under Pulsed Stress Condition

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (tOFF) and transition time (tTR = tRISE = tFALL). In particular, the shorter tOFF and tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer

High-temperature time-dependent gate breakdown of p-GaN HEMTs

In this article, we present an in-depth high-temperature analysis of the long-term gate reliability in GaN-based power high-electron-mobility transistors (HEMTs) with p-type gate. Three different isolation process options, aimed at improving the time-dependent gate breakdown (TDGB), are proposed and compared by means of constant voltage stress tests performed at different forward gate biases, temperatures, and geometries. In particular, depending on the gate bias and temperature, the breakdown event may occur along the active gate area or through the isolation region. The results show different voltage dependency for such two different failure locations; therefore, two field-acceleration fitting models are needed for the estimation of lifetime. Furthermore, the gate time-to-failure (TTF) shows a non-monotonous temperature dependency at given gate bias. More specifically, a positive and a negative T-derivatives are observed at relatively low and high temperatures, respectively, which are related to active gate area and isolation region failure, respectively

TCAD Modeling of the Dynamic VTH Hysteresis Under Fast Sweeping Characterization in p-GaN Gate HEMTs

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic VTH hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic VTH hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components

Gate reliability of p-GaN power HEMTs under pulsed stress condition

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (t(OF)F) and transition time (t(TR) = t(RISE) = t(FALL)). In particular, the shorter tOFF and tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer