Analysis of public procurement in Havlíčkův Brod between the years 2015-2019

The main topic of this bachelor’s thesis is analysis of public procurement in Havlíčkův Brod between the years 2015-2019. The first part contains theoretical terms, which are important for understanding of the analytical part. The main part is focused on dividing public procurement on the different basis of division. Practical part begins with the analysis of the budget of Havlíčkův Brod and then is followed by analysis of public procurement. The last part is dedicated to comparison of the results to the data about public procurement in the Czech republic.Hlavním tématem této bakalářské práce je analýza veřejných zakázek ve městě Havlíčkův Brod v letech 2015-2019. První kapitola se zaobírá teoretickou částí, ve které jsou vysvětlené základní pojmy důležité k pochopení analytické části práce. Pozornost je věnována hlavně rozdělení veřejných zakázek podle různých druhů dělení. Praktická část začíná analýzou rozpočtu Havlíčkova Brodu a poté následuje analýza veřejných zakázek. Poslední část je věnována porovnání výsledků analýzy s daty veřejných zakázek v České republice

ZrO2/InAlN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with InAlN Barrier of Different Compositions

We report on InAlN/GaN heterostructure metal-oxide-semiconductor field-effect transistors (MOSHFETs) with an InAlN barrier layer of different compositions (x(InN) 13, 17, and 21%) and ZrO2 gate-insulator/passivation. Static measurements yielded higher drain currents than those on unpassivated HFET counterparts and the currents increased with decreased x(InN). Post deposition annealing of the ZrO2 insulator had less influence on the static performance but remarkable changes were observed on the capacitance-voltage characteristics. The capacitance hysteresis in both channel depletion and barrier accumulation regions was significantly suppressed after annealing. This indicates a reduction of the interfacial trap states and of fixed charge in the oxide. Pulsed current-voltage measurements confirmed this conclusion-the gate lag of only similar to 80% was evaluated for 200 ns pulse width, independently on the composition of the InAlN barrier layer. These results support an application of high permittivity ZrO2 gate-insulator/passivation for the preparation of high-performance InAlN/GaN MOSHFETs. (C) 2013 The Japan Society of Applied Physic

GaAs Nanomembranes in the High Electron Mobility Transistor Technology

A 100 nm MOCVD-grown HEMT AlGaAs/InGaAs/GaAs heterostructure nanomembrane was released from the growth GaAs substrate by ELO using a 300 nm AlAs layer and transferred to sapphire. The heterostructure contained a strained 10 nm 2DEG In0.23Ga0.77As channel with a sheet electron concentration of 3.4 × 1012 cm−2 and Hall mobility of 4590 cm2V−1s−1, which was grown close to the center of the heterostructure to suppress a significant bowing of the nanomembrane both during and after separation from the growth substrate. The as-grown heterostructure and transferred nanomembranes were characterized by HRXRD, PL, SEM, and transport measurements using HEMTs. The InGaAs and AlAs layers were laterally strained: ~−1.5% and ~−0.15%. The HRXRD analysis showed the as-grown heterostructure had very good quality and smooth interfaces, and the nanomembrane had its crystalline structure and quality preserved. The PL measurement showed the nanomembrane peak was shifted by 19 meV towards higher energies with respect to that of the as-grown heterostructure. The HEMTs on the nanomembrane exhibited no degradation of the output characteristics, and the input two-terminal measurement confirmed a slightly decreased leakage current

Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors

The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements