Property Rights Protection and Investment: A Natural Experiment from China

This paper utilizes a natural experiment to examine the role of the protection of property rights in promoting investment. In order to explore a title-granting scheme in Shenzhen, China, I collect a sample of 83 listed SOE firms, with 32 of them holding about-to-be-entitled lands. Those landholders exhibit both a sharp short-term 7.8% additional increase in stock market price and a long-term 63% extra increase in investment, when compared with non-landholders, despite that there is no pre-event structural difference between the two. These increases in value are a result of having solved hold-up problems rather than a result of increased collateral values because those politically connected SOEs under analysis are financially unconstrained. Cross-sectionally, those firms with weaker pre-event protection against “hold-up” are associated with greater increases in share price and investment. Potentially, solving the hold-up problem of all unentitled land would bring about value of 2.2 Trillion RMB, almost triples Shenzhen's GDP in 2009

A Study of the Thematic Progression in Legal English Discourse

Being a special kind of language application, legal English enjoys its unique stylistic features, which are concise, logic, coherent and rigorous. It is quite meaningful and fruitful to study these features in discourse, which is the study of discourse analysis. System-functional linguistics provides distinguished perspective for discourse analysis, and once Halliday, the founder of System-functional linguistics, pointed out the system-functional grammar and its theories can be applied to legal English studies. This essay mainly discusses, analyzes and focuses on the discourse analysis of legal English and takes The Constitution of the United States of America as corpora to study from the perspective of Thematic Progression. It tries to explain how the Thematic Progression worked in developing the legal English discourse and how it helped legal English discourse to reach its features. Meanwhile it also hoped to inspire the application of linguistic theory into legal English studies

Financial repression in China and Global Economic Imbalances

We apply the old concept of financial repression, originally due to Mckinnon (1973) and Shaw (1973), to the Chinese financial system and argue that it might explain the country's current account surplus. In a two-country model, we show that financial repression in one country (China), modeled as a tax on domestic investment, would drive capital out and render its trading partner (US) with tax-arbitrage opportunity that is used to fund the latter's current-account deficit. Calibration demonstrate that the effect is quantitatively significant. In contrast to a common view, this intervention would decrease wages, employment and welfare in the financially-repressed country

Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event

In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation. Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event. In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure. Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device\u27s ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions. As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices. Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode

Distributed watermarking for secure control of microgrids under replay attacks

The problem of replay attacks in the communication network between Distributed Generation Units (DGUs) of a DC microgrid is examined. The DGUs are regulated through a hierarchical control architecture, and are networked to achieve secondary control objectives. Following analysis of the detectability of replay attacks by a distributed monitoring scheme previously proposed, the need for a watermarking signal is identified. Hence, conditions are given on the watermark in order to guarantee detection of replay attacks, and such a signal is designed. Simulations are then presented to demonstrate the effectiveness of the technique