ESSENTIAL POSTREPLICATIVE FUNCTIONS OF THE SMC5/6 COMPLEX

The structural maintenance of chromosomes (SMC) complex Smc5/6 is based on a heterodimer of two SMC subunits, Smc5 and Smc6, and six non-Smc element subunits, Nse1-6, all of which are essential for cell viability in most organisms. Smc5/6 safeguards genome integrity via different mechanisms, including stabilization of stalled replication forks, resolution of recombination intermediates, and maintenance of nucleolar integrity. However, the essential functions of Smc5/6 remain elusive. The aim of the present work was to understand when in the cell cycle the crucial functions of Smc5/6 are manifested and to identify them. Through the use of cell cycle regulated alleles, which enabled the restriction of various Smc5/6 subunits expression to either S or G2/M phases of the cell cycle, we uncovered that the essential roles are executed postreplicatively in G2/M. By further genetic screens, molecular approaches and genome-wide studies, we identified three chromosome topology and recombination-related processes that are crucially sensitive to low amounts of Smc5/6 specifically in G2/M. First, Smc5/6 plays a topological role affecting the formation and/or the resolution of Rad5-Mms2-Ubc13 chromatin structures that are later engaged by Sgs1-Top3-Rmi1. Second, Smc5/6 facilitates an epigenetic pathway that ensures silencing of specific loci, such as repetitive DNA regions, thereby preventing unrestrained recombination. Third, Smc5/6 has an anti-fragility function, facilitating replication through natural pausing elements and site-specific replication fork barriers and preventing their breakage in mitosis during chromosome segregation

DNA bending facilitates the error-free DNA damage tolerance pathway and upholds genome integrity

Abstract DNA replication is sensitive to damage in the template. To bypass lesions and complete replication, cells activate recombination-mediated (error-free) and translesion synthesis-mediated (error-prone) DNA damage tolerance pathways. Crucial for error-free DNA damage tolerance is template switching, which depends on the formation and resolution of damage-bypass intermediates consisting of sister chromatid junctions. Here we show that a chromatin architectural pathway involving the high mobility group box protein Hmo1 channels replication-associated lesions into the error-free DNA damage tolerance pathway mediated by Rad5 and PCNA polyubiquitylation, while preventing mutagenic bypass and toxic recombination. In the process of template switching, Hmo1 also promotes sister chromatid junction formation predominantly during replication. Its C-terminal tail, implicated in chromatin bending, facilitates the formation of catenations/hemicatenations and mediates the roles of Hmo1 in DNA damage tolerance pathway choice and sister chromatid junction formation. Together, the results suggest that replication-associated topological changes involving the molecular DNA bender, Hmo1, set the stage for dedicated repair reactions that limit errors during replication and impact on genome stability

The S phase checkpoint promotes the Smc5/6 complex dependent SUMOylation of Pol2, the catalytic subunit of DNA polymerase ε

Replication fork stalling and accumulation of single-stranded DNA trigger the S phase checkpoint, a signalling cascade that, in budding yeast, leads to the activation of the Rad53 kinase. Rad53 is essential in maintaining cell viability, but its targets of regulation are still partially unknown. Here we show that Rad53 drives the hyper-SUMOylation of Pol2, the catalytic subunit of DNA polymerase ε, principally following replication forks stalling induced by nucleotide depletion. Pol2 is the main target of SUMOylation within the replisome and its modification requires the SUMO-ligase Mms21, a subunit of the Smc5/6 complex. Moreover, the Smc5/6 complex co-purifies with Pol ε, independently of other replisome components. Finally, we map Pol2 SUMOylation to a single site within the N-terminal catalytic domain and identify a SUMO-interacting motif at the C-terminus of Pol2. These data suggest that the S phase checkpoint regulate Pol ε during replication stress through Pol2 SUMOylation and SUMO-binding abilit

Room-temperature THz imaging based on antenna-coupled MOSFET bolometer

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A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop-quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10E-12) at 60Gb/s. At this data rate, the CDR achieves +/- 600ppm frequency tracking range. The measured sinusoidal JTOL indicates a corner frequency of about 80MHz, with high frequency JTOL of 0.16UIpp at -5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit

A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507 +/- 0.717mm(2). Experimental results showing system performance are obtained using a (2(15)-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pith at a supply voltage of 0.8 V. The VD, implemented in an experimental chip fabricated in 14-nm CMOS FINFET, exploits set-partitioning principles and embedded per-survivor decision feedback to reduce implementation complexity and power consumption. The active area of the VD with 12 slices, each operating at one-eighth of the modulation rate, is 0.507 x 0.717 mm(2). Experimental results showing system performance are obtained by using a (2(15)-1)-bit pseudo-random binary sequence. The impact of the synchronization length and survivor path memory length on the detector design and system performance are shown. A new pipelined reduced-state sequence detector algorithm is presented for high-speed implementations. A novel speculative symbol timing recovery scheme is proposed. New simulation results are obtained to compare the performance of the Reed-Solomon (RS)-encoded 4-PAM scheme with that of the concatenated RS 4-D 5-PAM trellis-coded-modulation (TCM) scheme over an ideal band-limited additive-white-Gaussian-noise channel. Drawing on the results achieved for the VD, novel design techniques for a high-speed low-complexity eight-state 4-D 5-PAM TCM decoder is proposed