Low phase noise, high bandwidth frequency synthesis techniques

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 243-249).A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be <100kHz for adequate phase noise performance to be achieved. Using the proposed technique, quantization noise is reduced to the point where intrinsic noise sources (VCO, charge-pump, reference and PFD noise) ultimately limit noise performance. An analytical model that draws an analogy between fractional-N frequency synthesizers and MASH A digital-to-analog converters is proposed. Calculated performance of a synthesizer implementing the proposed quantization noise reduction techniques shows excellent agreement with simulation results of a behavioral model. Behavioral modeling techniques that progressively incorporate non-ideal circuit behavior based on SPICE level simulations are proposed. The critical circuits used to build the proposed synthesizer are presented.(cont.) These include a divider retiming circuit that avoids meta-stability related to synchronizing an asynchronous signal, a timing mismatch compensation block used by a dual divider path PFD, and a unit element current source design for reduced output phase noise. Measurement results of a prototype 0.18/m CMOS synthesizer show that quantization noise is suppressed by 29dB when the proposed synthesizer architecture is compared to 2nd order EA frequency synthesizer. The 1MHz closed loop bandwidth allows the synthesizer to be modulated by up to 1Mb/s GMSK data for use as a transmitter with 1.8GHz and 900MHz outputs. The analytical model is used to back extract on-chip mismatch parameters that are not directly measurable. This represents a new analysis technique that is useful in the characterization of fractional-N frequency synthesizers.by Scott Edward Meninger.Ph.D

MEMS electrostatic micropower generator for low frequency operation

Accepted versio

Power processing circuits for electromagnetic, electrostatic and piezoelectric inertial energy scavengers

Accepted versio

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially to the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a non-ferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state and thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation have been performed on fully-depleted silicon-on-insulator (FDSOI) FeFETs integrated on 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the non-ferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.Comment: 32 page

Using time delay in the nonlinear oscillations of magnetic levitation for simultaneous energy harvesting and vibration suppression

In this paper, the nonlinear oscillations of magnetic levitation in the presence of a time delay is investigated, with the purpose of simultaneous energy harvesting and vibration suppression. To harvest energy, a coil with seven layers of 36 gauge wire wound around the outer casing is utilized. Although the proposed control feedback consumes some power, the results show the harvestable power can be much larger than the consumed power, which makes the proposed concept feasible. The first-order perturbation method is utilized to examine the possibility of energy harvesting and vibration suppression for different selections of the delay parameters, the distances between the magnets and the external load resistances. In addition, the stability map of the time-delayed control is analytically determined. The influence of the time delay parameters chosen from Single Periodic Solutions (SPS) and Multiple Periodic Solutions (MPS) on the vibration and power amplitudes is studied. It is shown that a point chosen from the MPS region enables the system to harvest power over a broad range of excitation frequencies. Also, the effect of the distance between the magnets on the frequency response of the system is examined. In addition, to select the optimum value for the distance between the magnets for different values of the time delay parameters, a parameter called the Perfection Rate (PR), which reflects both the electrical and mechanical behavior of the system, is used. Finally, it is shown that the presence of the time delay and a point chosen from the MPS region enables the system to harvest more power over a broad range of excitation frequency and to suppress higher levels of vibration, than for a point chosen from the SPS region and without time delay

MENJADI PRIBADI UTUH

156 hlm;14.5cm x 21c

Low power controller for a microelectromechanical based energy converter

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 81-82).The trend in modern VLSI design towards low power DSP and sensing applications creates an opportunity for the development of self-powered systems based on harvesting ambient energy. Several different ambient sources have already been exploited. With advances in microelectromechanical (MEMS) technology, it is possible to implement a self powered system-on-a-chip with the MEMS device acting as the energy transducer in the form of a variable capacitor, with conversion controlled by employing low power digital control techniques. This thesis explores the design of such an energy converter. The theory behind the conversion process will be discussed, including the presentation of a mathematical model for the system. The design of a programmable delay line based digital controller and optimization of the accompanying complementary power switches is reviewed. Results from the fabricated controller are presented and discussed. The design of a self-locking controller, which is based on the present architecture, but uses a new energy feedback technique to phase lock to maximal energy transfer, is presented.by Scott Meninger.S.M

Penicillin skin testing in methicillin-sensitive staphylococcus aureus bacteremia: A cost-effectiveness analysis.

BackgroundBeta-lactams are the mainstay for treating methicillin-susceptible Staphylococcus aureus (MSSA) infections complicated by bacteremia due to superior outcomes compared with vancomycin. With approximately 11% of inpatients reporting a penicillin (PCN) allergy, many patients receive suboptimal treatment for MSSA bacteremia.ObjectiveEvaluate the cost-effectiveness of penicillin skin testing (PST) in adult patients with self-reported PCN allergy in an inpatient setting undergoing treatment for MSSA bacteremia.MethodsA decision analytic model was developed comparing an acute care PST intervention to a scenario with no confirmatory allergy testing. The primary outcome was the incremental cost-effectiveness ratio (ICER) from the health-sector perspective over a 1-year time horizon using quality-adjusted life years (QALYs) as the measure for effectiveness. One-way and probabilistic sensitivity analyses were conducted to assess the uncertainty of the ICER estimation.ResultsOver a 1-year time horizon, PST services applied to all MSSA bacteremia patients reporting a PCN-allergy would result in a cost per patient of $12,559 and 0.73 QALYs while no PST services would have a higher cost per patient of$13,219 and 0.66 QALYs per patient. This resulted in a cost-effectiveness estimate of -$9,429 per QALY gained. Varying the cost of implementing PST services determined a break-even point of$959.98 where any PST cost less than this amount would actually be cost saving.ConclusionsPatients reporting a PCN allergy on admission may receive sub-optimal alternative therapies to beta-lactams, such as vancomycin, for MSSA bacteremia. This economic analysis demonstrates that inpatient PST services confirming PCN allergy are cost-effective for patients with MSSA bacteremia