The Liberalization Of Shibor And The Economic Fundamentals Of House Price Growth In China

This paper uses data collected from the National Interbank Funding Center of China, the People’s Bank of China, the National Bureau of Statistics, and Bloomberg starting in October 2006 through 2013 to test the economic fundamental’s affecting the housing market in Shanghai, particularly interest rates. This study finds that the 6- month duration Shibor has a negative and significant correlation with house price growth in Shanghai when lagged 4 months. The analysis continues by examining other economic fundamentals affecting house price growth, finding growth in inflation, the money supply and Shanghai real estate investment to have significant, positive relationships with the housing market in China. GDP and the national state balance, on the other hand, have negative and significant relationships with house price growth. The Shanghai stock exchange was found to have no significant impact on the housing market over the time period. The sample period is limited to 87 observations due to the relatively recent development of Shibor for a benchmark interest rate

A Scalable Compact Model for the Static Drain Current of Graphene FETs

The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures IV experimental dependencies induced by geometrical scaling effects for graphene transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions, are thoroughly investigated, and semi?empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research labs. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and hence, can contribute to the update of GFET technology from the research level to massive industry production

Velocity Saturation effect on Low Frequency Noise in short channel Single Layer Graphene FETs

Graphene devices for analog and RF applications are prone to Low Frequency Noise (LFN) due to its upconversion to undesired phase noise at higher frequencies. Such applications demand the use of short channel graphene transistors that operate at high electric fields in order to ensure a high speed. Electric field is inversely proportional to device length and proportional to channel potential so it gets maximized as the drain voltage increases and the transistor length shrinks. Under these conditions though, short channel effects like Velocity Saturation (VS) should be taken into account. Carrier number and mobility fluctuations have been proved to be the main sources that generate LFN in graphene devices. While their contribution to the bias dependence of LFN in long channels has been thoroughly investigated, the way in which VS phenomenon affects LFN in short channel devices under high drain voltage conditions has not been well understood. At low electric field operation, VS effect is negligible since carriers velocity is far away from being saturated. Under these conditions, LFN can be precicely predicted by a recently established physics-based analytical model. The present paper goes a step furher and proposes a new model which deals with the contribution of VS effect on LFN under high electric field conditions. The implemented model is validated with novel experimental data, published for the first time, from CVD grown back-gated single layer graphene transistors operating at gigahertz frequencies. The model accurately captures the reduction of LFN especially near charge neutrality point because of the effect of VS mechanism. Moreover, an analytical expression for the effect of contact resistance on LFN is derived. This contact resistance contribution is experimentally shown to be dominant at higher gate voltages and is accurately described by the proposed model.Comment: Main Manuscript:10 pages, 6 figure

Understanding the Bias Dependence of Low Frequency Noise in Sin-gle Layer Graphene FETs

This letter investigates the bias-dependent low frequency noise of single layer graphene field-effect transistors. Noise measurements have been conducted with electrolyte-gated graphene transistors covering a wide range of gate and drain bias conditions for different channel lengths. A new analytical model that accounts for the propagation of the local noise sources in the channel to the terminal currents and voltages is proposed in this paper to investigate the noise bias dependence. Carrier number and mobility fluctuations are considered as the main causes of low frequency noise and the way these mechanisms contribute to the bias dependence of the noise is analyzed in this work. Typically, normalized low frequency noise in graphene devices has been usually shown to follow an M-shape dependence versus gate voltage with the minimum near the charge neutrality point (CNP). Our work reveals for the first time the strong correlation between this gate dependence and the residual charge which is relevant in the vicinity of this specific bias point. We discuss how charge inhomogeneity in the graphene channel at higher drain voltages can contribute to low frequency noise; thus, channel regions nearby the source and drain terminals are found to dominate the total noise for gate biases close to the CNP. The excellent agreement between the experimental data and the predictions of the analytical model at all bias conditions confirms that the two fundamental 1/f noise mechanisms, carrier number and mobility fluctuations, must be considered simultaneously to properly understand the low frequency noise in graphene FETs. The proposed analytical compact model can be easily implemented and integrated in circuit simulators, which can be of high importance for graphene based circuits design.Comment: 18 pages, 10 figure

Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors

transformatiu CRUE-CSICUTP en procés de revisióAltres ajuts: GraphCAT project reference 001-P-001702The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided

Bias Dependent Variability of Low Frequency Noise in Single Layer Graphene FETs

Low-frequency noise (LFN) variability in graphene transistors (GFETs) is for the first time researched in this work. LFN from an adequate statistical sample of long-channel solution-gated single-layer GFETs is measured in a wide range of operating conditions while a physics-based analytical model is derived that accounts for the bias dependence of LFN variance with remarkable performance. It is theoretically proved and experimentally validated that LFN deviations in GFETs stem from physical mechanisms that generate LFN. Thus, carrier number DN due to trapping/detrapping process and mobility fluctuations Dm which are the main causes of LFN, define its variability likewise as its mean value. DN accounts for an M-shape of normalized LFN variance versus gate bias with a minimum at the charge neutrality point (CNP) as it was the case for normalized LFN mean value while Dm contributes only near the CNP for both variance and mean value. Trap statistical nature is experimentally shown to differ from classical Poisson distribution at silicon-oxide devices, and this is probably caused by electrolyte interface in GFETs under study. Overall, GFET technology development is still in a premature stage which might cause pivotal inconsistencies affecting the scaling laws in GFETs of the same process