Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e. critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst-case precision of 99.999%, energy savings up to 36% are demonstrated compared to exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation

Combining Structural and Timing Errors in Overclocked Inexact Speculative Adders

Worst-case design is used in IoT devices and high performance data centers to ensure reliability, leading to a power efficiency loss. Recently, approximate computing has been proposed to trade off accuracy for efficiency. In this paper, we use Inexact Speculative Adders, which redesign the adder architecture to shorten its critical path and improve performance, but introduces controlled structural errors. On the other hand, overclocking is used to reduce conservative timing guardbands but could normally introduce catastrophic timing errors, we thus apply a supervised learning model to overclock speculative adders and predict their timing errors. We build a methodology to combine both structural and timing errors and analyze how they interplay with each other to limit the overal errors

Single walled carbon nanotube/Si heterojunctions for high responsivity photodetectors

Single Walled Carbon Nanotube/n-Si (SWCNT/n-Si) hetero-junctions have been obtained by depositing SWCNT ultra-thin films on the surface of an n-Si substrate by dry transfer method. The as obtained junctions are photo sensitive in the measured wavelength range (300 nm-1000 nm) and show zero bias responsivity and detectivity values of the order of 1 A/W and 1014 Jones respectively, which are higher than those previously observed in carbon based devices. Moreover, under on-off light excitation, the junctions show response speed as fast as 1 μs or better and noise equivalent powers comparable to commercial Si photomultipliers. Current-voltage measurements in dark and under illumination suggest that the devices consist of Schottky and semiconductor/semiconductor junctions both contributing to the fast and high responses observed

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from correct behavior for lower resource usage. We present, for the first time, a synthesis of research results on computing systems that only make as many errors as their end-to-end applications can tolerate. The results span the disciplines of computer-aided design of circuits, digital system design, computer architecture, programming languages, operating systems, and information theory. Rather than over-provisioning the resources controlled by each of these layers of abstraction to avoid errors, it can be more efficient to exploit the masking of errors occurring at one layer and thereby prevent those errors from propagating to a higher layer.We demonstrate the potential benefits of end-to-end approaches using two illustrative examples. We introduce a formalization of terminology that allows us to present a coherent view across the techniques traditionally used by different research communities in their individual layer of focus. Using this formalization, we survey tradeoffs for individual layers of computing systems at the circuit, architecture, operating system, and programming language levels as well as fundamental information-theoretic limits to tradeoffs between resource usage and correctness

Tuning Multi/Pluri-Potent Stem Cell Fate by Electrospun Poly(l-lactic acid)-Calcium-Deficient Hydroxyapatite Nanocomposite Mats

In this study, we investigated whether multipotent (human-bone-marrow-derived mesenchymal stem cells [hBM-MSCs]) and pluripotent stem cells (murine-induced pluripotent stem cells [iPSCs] and murine embryonic stem cells [ESCs]) respond to nanocomposite fibrous mats of poly­(l-lactic acid) (PLLA) loaded with 1 or 8 wt % of calcium-deficient nanohydroxyapatite (d-HAp). Remarkably, the dispersion of different amounts of d-HAp to PLLA produced a set of materials (PLLA/d-HAp) with similar architectures and tunable mechanical properties. After 3 weeks of culture in the absence of soluble osteogenic factors, we observed the expression of osteogenic markers, including the deposition of bone matrix proteins, in multi/pluripotent cells only grown on PLLA/d-HAp nanocomposites, whereas the osteogenic differentiation was absent on stem-cell-neat PLLA cultures. Interestingly, this phenomenon was confined only in hBM-MSCs, murine iPSCs, and ESCs grown on direct contact with the PLLA/d-HAp mats. Altogether, these results indicate that the osteogenic differentiation effect of these electrospun PLLA/d-HAp nanocomposites was independent of the stem cell type and highlight the direct interaction of stem cell-polymeric nanocomposite and the mechanical properties acquired by the PLLA/d-HAp nanocomposites as key steps for the differentiation process