Modeling and Simulation of a Hard Real-Time Processor

Hard real-time systems are increasingly used in various areas of human activity justifying their implementation by means of specialized solutions, mostly of a suitable hardware/software combination. A frequently adopted approach to the realization of the hardware part is based on ASIC, usually a “general purpose” processor which operates according to real-time constraints. In this work the modeling of a processor for the hard real-time domain is described. It is structured as a collection of “task processors” being supervised by another one dedicated to the “kernel” functions. Specifically the behavior of the task processors is modeled using VHDL and subsequently simulated and tested. The paper also addresses the modeling process by determining the detailed requirements on the behavior of the task processor. The outcome of this step influenced the modeling process as the tools used were of restricted functionality and processor behavior enforced a particular decomposition. Because of a restricted VHDL subset available, it was necessary to model the task processor on the lowest level of behavioral abstraction. The task processor has been tested against chosen test programs written in an appropriate assembly language being specially developed for this purpose

An Experiment in Design and Analysis of Real-Time Applications

In the paper some experiences of joining two methodologies, which were originally independently developed in different institutions, with the goal to overcome the possible discrepancies due to the separate design of the hardware and the software part of an embedded real-time application are presented. Based on Multiprocessor PEARL, Specification PEARL has been developed in FERI, Maribor. Hardware and system architecture of an application can be described and gradually refined. Application software can be designed using LACATRE tool, developed at INSA, Lyon. Decisions about the application design taken in each tool have influence to the ones taken in the other, thus allowing for parallel design of both parts. Both designs are subsequently verified and eventually joined for feasibility estimation by co-simulation. The application program is coded using the ObjectPEARL language. The real-time system design cycle is closed by the execution time analysis and measurements upon which it is then considered about further program and/or hardware part reconfiguration. This feature is supported by the specific compiler, which includes the execution time analyser. The article reports on the work that was done in the framework of the PROTEUS project in co-operation of the teams from FERI Maribor, Slovenia, and INSA de Lyon, France

Specification PEARL constructs for embedded real-time systems co-design

In the article a HW/SW co-design methodology is presented, which enables early reasoning about system integration as well as verification of the designs. Specification PEARL methodology is based on a specification language with the same name, whose ori-gins are in the standard Multiprocessor PEARL language. It has been enhanced by addi-tional components for asymmetrical multiprocessor systems design as well as by additional parameters for RTOS parameterisation and feasibility analysis. Timed State Transition Diagrams have been introduced for program/task modelling, supporting the PEARL pro-cess model. The resulting task models are easily translated to PEARL task prototypes. The methodology and its specification language components are being presented

Improving integrity of embedded computers in control

This paper gives an overview of a holistic project dealing with the consistent design of embedded control systems falling into the first level of safety integrity requirements (SIL l) (IEC, 1998). It shows how existing methods can be adapted and reasonably employed, whenever possible, without having to resort to new innovations. Firstly, the hardware issues are dealt with and extensively elaborated, particularly the peripheral interfaces with integrated processing capabilities. Secondly, the proven correct real-time operating system executing on its own dedicated processor is briefly addressed, and finally, programming issues including descriptions of the specific programming language, time bounded handling of exceptions, and how to deal with temporal overload

A reconfiguration pattern for distributed embedded systems

A reconfiguration pattern for UML-based projects of embedded (real-time) systems is defined. It enables to set up hardware/software configurations, and to specify conditions and methods for dynamic reconfiguration. The reconfiguration pattern was inspired by the reconfiguration management solution of the Specification PEARL methodology, which is based on the standard for Multiprocessor PEARL whose original idea it was to extend the language to enable the programming of distributed real-time applications in PEARL. In Specification PEARL, the possibility for abstract descriptions of hardware and software architectures and for defining mappings from software to hardware components has been enhanced in correspondence with the standard. Here, a UML pattern for reconfiguration management in distributed embedded applications based on concepts from Specification PEARL is presented. Its behavioural, structural and functional aspects are outlined. It addresses stereotype entities from the Specification PEARL language, which were joined in a UML profile, and outlines the related reconfiguration management mechanisms, which were carried over to the mentioned UML pattern. The proposed reconfiguration pattern is to facilitate the development of distributed embedded application in UML with consistent and temporally predictable reconfiguration support. It should also support and enhance the applicationsć flexibility and portability

Implementation of hard real-time embedded control systems

Although the domain of hard real-time systems has been thoroughly elaborated in the academic sphere, embedded computer control systems - being an important in mechatronic design - are seldom dealt with consistemntly. Often, off-the-shelf computer systems are used, with no guarantee that they will be able to meet the requirements specified. In this paper, a design for embedded control systems is presented. particulary, the paper deals with the hardware architecture and design details, the operating sustem, and the high-level real-time language support. It is shown how estimates of process run-times necessary for schedulability analysis can be acquired on the basis of deterministic behavior of the hardware platform