A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.Comment: ISBN:1-4244-0921-

A Design Methodology for Space-Time Adapter

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.Comment: ISBN : 978-1-59593-606-

Out- versus in-plane magnetic anisotropy of free Fe and Co nanocrystals: tight-binding and first-principles studies

We report tight-binding (TB) and Density Function Theory (DFT) calculations of magnetocrystalline anisotropy energy (MAE) of free Fe (body centerd cubic) and Co (face centered cubic) slabs and nanocrystals. The nanocrystals are truncated square pyramids which can be obtained experimentally by deposition of metal on a SrTiO$_3$(001) substrate. For both elements our local analysis shows that the total MAE of the nanocrystals is largely dominated by the contribution of (001) facets. However, while the easy axis of Fe(001) is out-of-plane, it is in-plane for Co(001). This has direct consequences on the magnetic reversal mechanism of the nanocrystals. Indeed, the very high uniaxial anisotropy of Fe nanocrystals makes them a much better potential candidate for magnetic storage devices.Comment: 8 pages, 7 figure

Cystatine C plasmatique chez le chat, intervalle de références, variations dans l'insuffisance rénale

La cystatine C est un marqueur d'insuffisance rénale plus sensible et plus précoce que la créatinine chez l'homme. Chez le chien, sa concentration augmente aussi lors d'insuffisance rénale. Le but de cette étude est savoir si Pl-Cystatine C peut être utilisée dans le diagnostic de l'insuffisance rénale chez le chat. La concentration plasmatique en cystatine C a été mesurée par une technique PETIA sur automate Cobas Mira Plus. Chez les sujets sains (n = 99), la distribution de Pl-Cystatine C n'était ni gaussienne ni log-gaussienne. L'intervalle des valeurs usuelles calculé de manière non-paramétrique était de 0,34 et 4,11 mg/1. Chez les 75 chats présentant de signes cliniques et biologiques d'insuffisance rénale, Pl-Cystatine C était significativement élevée (p<0,05) avec des extrêmes à 0,35 et 9,52 mg/1, cependant 60 chats avaient des valeurs inférieures à 4,11 mg/1. La corrélation entre la cystatine et la créatinine ou l'urée était faible quel que soit le groupe. L'intervalle des valeurs usuelles chez le chat est plus large que chez le chien ou l'homme. Cela pourrait être du à une fixation aspécifique des anticorps utilisés dans le dosage, à d'autres protéines plasmatiques. Cette incertitude analytique ne permet donc pas d'utiliser la cystatine C chez le chat comme moyen diagnostique de l'insuffisance rénale

A batch scheduler with high level components

In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emphasizes on low software complexity by using high level tools. The global architecture is built upon the scripting language Perl and the relational database engine Mysql. The goal of the project OAR is to prove that it is possible today to build a complex system for ressource management using such tools without sacrificing efficiency and scalability. Currently, our system offers most of the important features implemented by other batch schedulers such as priority scheduling (by queues), reservations, backfilling and some global computing support. Despite the use of high level tools, our experiments show that our system has performances close to other systems. Furthermore, OAR is currently exploited for the management of 700 nodes (a metropolitan GRID) and has shown good efficiency and robustness

M\'ethodologie de mod\'elisation et d'impl\'ementation d'adaptateurs spatio-temporels

The re-use of pre-designed blocks is a well-known concept of the software development. This technique has been applied to System-on-Chip (SoC) design whose complexity and heterogeneity are growing. The re-use is made thanks to high level components, called virtual components (IP), available in more or less flexible forms. These components are dedicated blocks: digital signal processing (DCT, FFT), telecommunications (Viterbi, TurboCodes),... These blocks rest on a model of fixed architecture with very few degrees of personalization. This rigidity is particularly true for the communication interface whose orders of acquisition and production of data, the temporal behavior and protocols of exchanges are fixed. The successful integration of such an IP requires that the designer (1) synchronizes the components (2) converts the protocols between "incompatible" blocks (3) temporizes the data to guarantee the temporal constraints and the order of the data. This phase remains however very manual and source of errors. Our approach proposes a formal modeling, based on an original Ressource Compatibility Graph. The synthesis flow is based on a set of transformations of the initial graph to lead to an interface architecture allowing the space-time adaptation of the data exchanges between several components

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

4 pagesInternational audienceFor high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques

Application of a design space exploration tool to enhance interleaver generation

This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). Design space exploration is then performed through associated tools, to synthesize a STAR component under time-to-market constraints. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver

An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture

International audienceA practical and feasible solution for LDPC decoder is to design partially-parallel hardware architecture. These architectures are efficient in terms of area, cost, flexibility and performances. However, this type of architecture is complex to design since concurrent read and write accesses to data have to be performed at each time instance without any conflict. To solve this memory mapping problem, we present in this paper, an original approach based on a tripartite graph modeling and a modified edge coloring algorithm to design parallel LDPC interleaver architecture

Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach

International audienceParallel hardware architecture proves to be an excellent compromise between area, cost, flexibility and high throughput in the hardware design of LDPC decoder. However, this type of architecture suffers from memory mapping problem: concurrent read and write accesses to data have to be performed at each time instance without any conflict. In this paper, we present an original approach based on the tanner graph modeling and a modified bipartite edge coloring algorithm to design parallel LDPC interleaver architecture