Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study

AbstractSo far, multiple classifier systems have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power. Indeed, compared to software implementations, hardware accelerators guarantee higher throughput and lower latency. Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices. For this reason, in this paper, we exploit approximate computing design paradigm to trade hardware area overhead off for classification accuracy. In particular, starting from trained DT models and employing precision-scaling technique, we explore approximate decision tree variants by means of multiple objective optimization problem, demonstrating a significant performance improvement targeting field-programmable gate array devices

Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems

The current trend in energy resources shapes how computing systems will address new challenges in the following years. As a matter of fact, following the current trend, by 2040, computers will require more energy than the world’s resources can generate. In the very upcoming future, by 2025, data centers alone will consume 20% of all available electricity. A similar trend already impacts the communications side where, for example, energy consumption in mobile broadband networks and mobile terminals is comparable to data centers. These trends can only accelerate by broadening the spectrum of possible mobile applications to the Internet of Things (IoT), which will connect 50 billion devices through wireless connections to the cloud infrastructure within a few years

Decision Tree-Based Multiple Classifier Systems: An FPGA Perspective

Combining a hardware approach with a multiple classifier method can deeply improve system performance, since the multiple classifier system can successfully enhance the classification accuracy with respect to a single classifier, and a hardware implementation would lead to systems able to classify samples with high throughput and with a short latency. To the best of our knowledge, no paper in the literature takes into account the multiple classifier scheme as additional design parameter, mainly because of lack of efficient hardware combiner architecture. In order to fill this gap, in this paper we will first propose a novel approach for an efficient hardware implementation of the majority voting combining rule. Then, we will illustrate a design methodology to suitably embed in a digital device a multiple classifier system having Decision Trees as base classifiers and a majority voting rule as combiner. Bagging, Boosting and Random Forests will be taken into account. We will prove the effectiveness of the proposed approach on two real case studies related to Big Data issues

Securing Embedded Digital Systems For In-Field Applications

Nowadays, special purpose embedded system design relies on the availability of the hardware configurable technology. Space missions, aerospace defense, high performance computing and networking applications benefit from the adoption of field programamble gate arrays (FPGAs) as they provide high degrees of flexibility, fast time-to-market, and low overall non-recurring engineering costs (NRE), but they almost lack in providing security mechanisms to protect intellectual properties (IPs) configured on them. The FPGA programming process is accomplished by a configuration file, so called bitstream and hacking attempts can succeed in either cloning the bitstream or, by means of reverse engineering techniques, extracting from it some IPs. Furthermore, through the program- ming interface, a malicious bitstream can be injected such that the device is reconfigured with a new configuration which overwrites the previous one. The consequences could be really dangerous, not only for the application, but also because they can cause money loss. Since the FPGA programming is pretty much like to software developing process, some existing techniques can be adopted in order to secure the device, mainly involving cryptography primitives. They can guarantee authenticity and confidentiality by ex- ploiting a key stored in each device, but they can be successfully hacked with physical attacks on the device, such that the key is discovered or the configuration file in plain is extracted once deciphered. Recently in the literature, a new technique has been intro- duced to cope with these issues, called Physically Unclonable Function, since it provides a unique, unclonable and unpredictable hardware fingerprint. Even with the best design effort, PUFs suffer from instability such that their values are variable in time. To face with these issues, this doctoral thesis shows the research activity conducted with the aim of exploring the security threats that characterize the configurable devices and of defining involved roles and new techniques for a design methodology able to guaran- tee several security attributes, demonstrating the feasibility with a very extended case study, based on a mobile scenario in which high throughput traffic analyzer IP core is distributed to a reconfigurable devices population

Editorial : Special Issue on Design, Technology, and Test of Integrated Circuits and Systems

International audienc

Formal Design Space Exploration for memristor-based crossbar architecture

International audienceThe unceasing shrinking process of CMOS technology is leading to its physical limits, impacting several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of promising technologies. Several works have been proposed so far, describing how to synthesize boolean logic functions on memristors-based crossbar architecture. However, depending on the synthesis parameters, different architectures can be obtained. Design Space Exploration (DSE) is therefore mandatory to help and guide the designer in order to select the best crossbar configuration. In this paper, we present a formal DSE approach. The main advantage is that it does not require any simulation and thus it avoids any runtime overheads. Preliminary results show the huge gain in runtime compared to simulation-based DSE