Quirks and Challenges in the Design and Verification of Efficient, High-Load Real-Time Software Systems

International audienceExisting concepts for ensuring the correctness of the timing behavior of real-time systems are often based on schedulability analysis methods using exact proofs. Due to the complexity of the scheduling problem, today typically worst case approximations are used to judge the reliability of the timing behavior in software systems. In industrial practice, however, this leads to large safety margins in the design of products which are commercially unacceptable in many application domains. For such highly-efficient systems, schedulability analysis methods that are too pessimistic are of limited benefit. As a consequence, penetration of real-time analysis is suboptimal in the industrial software development, which possibly leads to insufficient quality of the developed products. Therefore, new approaches are needed to support the design and validation of high-load real-time systems with an average CPU load of 90% or above to improve the situation

Deterministic Execution Sequence in Component Based Multi-Contributor Powertrain Control Systems

International audienceModern complex control applications, e.g. engine management systems, typically are built using a component based architecture, enabling the reuse of components and allowing to manage the complexity of the application in terms of functional content, size and interfaces. This approach of independently developed components is supported by the concepts available in AUTOSAR and therefore can be expected to gain increasing importance. However, due to the nature of the task of control applications there still is a strong coupling between individual parts of the components resulting in signal chains and consequently in sequencing requirements. The challenge to get such execution sequences implemented correctly is increased, as often the components are delivered by different and external parties. Our approach extends the idea of functional partitioning of the application into the time domain by defining a system of phases with a fixed sequence and a defined content. This allows to design components right from the beginning into this sequencing frame like they are designed today into the component partitioning frame and to define a system sequencing across different suppliers

Experiences with HPX on embedded real-time systems

Recently more and more embedded devices use multi-core processors. For example, the current generation of high-end engine-control units exhibit triple-core processors. To reliably exploit the parallelism of these cores, an advanced programming environment is needed, such as the current C++17 Standard, as well as the upcoming C++20 Standard. Using C++ to cooperatively parallelize software is comprehensively investigated, but not in the context of embedded multi-core devices with real-time requirements. For this paper we used two algorithms from Continental AG's powertrain which are characteristic for real-time embedded devices and examined the effect of parallelizing them with C++17/20, represented by HPX as a C++17/20 runtime implementation. Different data sizes were used to increase the execution times of the parallel sections. According to Gustafson's Law, with these increased data sizes, the benefit of parallelization increases and greater speed-ups are possible. When keeping Continental AG's original data sizes, HPX is not able to reduce the execution time of the algorithms