A New Process for Fabricating Random Silicon Nanotips

An improved process for the fabrication of random arrays of silicon nanotips has been demonstrated to be feasible. Relative to other such processes, this process offers advantages of low cost and simplicity. Moreover, this process can readily be combined with other processes used to fabricate integrated circuits and other monolithic silicon structures. Arrays of silicon nanotips are subjects of research and development efforts directed toward utilizing them as field emitters in flat-panel displays, vacuum microelectronics, and microwave devices. Other silicon-nanotip-fabrication processes developed thus far predominantly include lithography, etching, and/or elaborate deposition steps followed by oxide sharpening steps and are both process intensive as well as expensive. In addition to being cheaper and simpler, the present process can efficiently produce silicon nanotips that range in height from a few microns to several tens of microns and are distributed over large areas. The process mentioned here can be summarized as consisting of (1) the growth of micro-etch masks on a silicon substrate, followed by (2) etching away of the masks, along with some of the substrate, to make an array of sharp tips. In the first step of the process, a cleaned silicon substrate is subjected to reactive ion etching (RIE) in a certain mixture of oxygen and carbon tetrafluoride under radio-frequency excitation. This process step results in the growth of fluorine based compounds in the form of stumps randomly distributed on the substrate. These stumps are known in the art as polymer RIE grass. The dimensions of these stumps are of the order of hundreds of nanometers, the exact values depending on process time and gas composition. The areal density of the stumps decreases with increasing process time as they grow and merge with neighboring stumps. These stumps constitute the micro-etch masks for the next step of the process. In the second step of the process, the substrate covered with the microetch masks is subjected to deep reactive ion etching (DRIE) process, which consists of cycles of reactive ion etching alternating with passivation (the Bosch process). The gas used in the etching substeps is sulfur hexafluoride (SF6); the gas used in the passivation substeps is octafluorocyclobutane (C4F8). The portions of the substrate directly under the RIE grass stubs are etched more slowly than are the portions between the stubs. Hence, what remains at the end of the process, after the stubs and parts of the substrate have been etched away, are silicon spikes where the stubs were (see figure). In a variation of the process, one starts with a silicon or silicon-on-insulator substrate with the intent to etch through the full thickness of the substrate. That is to say, one chooses the thickness so that the DRIE step releases individual nanotips. Such individual silicon nanotips may have utility as microscopic probes in biomedical applications

Radiation-Insensitive Inverse Majority Gates

To help satisfy a need for high-density logic circuits insensitive to radiation, it has been proposed to realize inverse majority gates as microscopic vacuum electronic devices. In comparison with solid-state electronic devices ordinarily used in logic circuits, vacuum electronic devices are inherently much less adversely affected by radiation and extreme temperatures. The proposed development would involve state-of-the-art micromachining and recent advances in the fabrication of carbon-nanotube-based field emitters. A representative three-input inverse majority gate would be a monolithic, integrated structure that would include three gate electrodes, six bundles of carbon nanotubes (serving as electron emitters) at suitable positions between the gate electrodes, and an overhanging anode. The bundles of carbon nanotubes would be grown on degenerately doped silicon substrates that would be parts of the monolithic structure. The gate electrodes would be fabricated as parts of the monolithic structure by means of a double-silicon-on-insulator process developed at NASA's Jet Propulsion Laboratory. The tops of the bundles of carbon nanotubes would lie below the plane of the tops of the gate electrodes. The particular choice of shapes, dimensions, and relative positions of the electrodes and bundles of carbon nanotubes would provide for both field emission of electrons from the bundles of carbon nanotubes and control of the electron current to obtain the inverse majority function, which is described in the paper

Fabricating Large-Area Sheets of Single-Layer Graphene by CVD

This innovation consists of a set of methodologies for preparing large area (greater than 1 cm(exp 2)) domains of single-atomic-layer graphite, also called graphene, in single (two-dimensional) crystal form. To fabricate a single graphene layer using chemical vapor deposition (CVD), the process begins with an atomically flat surface of an appropriate substrate and an appropriate precursor molecule containing carbon atoms attached to substituent atoms or groups. These molecules will be brought into contact with the substrate surface by being flowed over, or sprayed onto, the substrate, under CVD conditions of low pressure and elevated temperature. Upon contact with the surface, the precursor molecules will decompose. The substituent groups detach from the carbon atoms and form gas-phase species, leaving the unfunctionalized carbon atoms attached to the substrate surface. These carbon atoms will diffuse upon this surface and encounter and bond to other carbon atoms. If conditions are chosen carefully, the surface carbon atoms will arrange to form the lowest energy single-layer structure available, which is the graphene lattice that is sought. Another method for creating the graphene lattice includes metal-catalyzed CVD, in which the decomposition of the precursor molecules is initiated by the catalytic action of a catalytic metal upon the substrate surface. Another type of metal-catalyzed CVD has the entire substrate composed of catalytic metal, or other material, either as a bulk crystal or as a think layer of catalyst deposited upon another surface. In this case, the precursor molecules decompose directly upon contact with the substrate, releasing their atoms and forming the graphene sheet. Atomic layer deposition (ALD) can also be used. In this method, a substrate surface at low temperature is covered with exactly one monolayer of precursor molecules (which may be of more than one type). This is heated up so that the precursor molecules decompose and form one monolayer of the target material

Arrays of Bundles of Carbon Nanotubes as Field Emitters

Experiments have shown that with suitable choices of critical dimensions, planar arrays of bundles of carbon nanotubes (see figure) can serve as high-current-density field emitter (cold-cathode) electron sources. Whereas some hot-cathode electron sources must be operated at supply potentials of thousands of volts, these cold-cathode sources generate comparable current densities when operated at tens of volts. Consequently, arrays of bundles of carbon nanotubes might prove useful as cold-cathode sources in miniature, lightweight electron-beam devices (e.g., nanoklystrons) soon to be developed. Prior to the experiments, all reported efforts to develop carbon-nanotube-based field-emission sources had yielded low current densities from a few hundred microamperes to a few hundred milliamperes per square centimeter. An electrostatic screening effect, in which taller nanotubes screen the shorter ones from participating in field emission, was conjectured to be what restricts the emission of electrons to such low levels. It was further conjectured that the screening effect could be reduced and thus emission levels increased by increasing the spacing between nanotubes to at least by a factor of one to two times the height of the nanotubes. While this change might increase the emission from individual nanotubes, it would decrease the number of nanotubes per unit area and thereby reduce the total possible emission current. Therefore, to maximize the area-averaged current density, it would be necessary to find an optimum combination of nanotube spacing and nanotube height. The present concept of using an array of bundles of nanotubes arises partly from the concept of optimizing the spacing and height of field emitters. It also arises partly from the idea that single nanotubes may have short lifetimes as field emitters, whereas bundles of nanotubes could afford redundancy so that the loss of a single nanotube would not significantly reduce the overall field emission

Improved Photoresist Coating for Making CNT Field Emitters

An improved photoresist-coating technique has been developed for use in the fabrication of carbon-nanotube- (CNT) based field emitters is described. The improved photoresist coating technique overcomes what, heretofore, has been a major difficulty in the fabrication process

Carbon nanotube vacuum gauges with wide-dynamic range and processes thereof

A miniature thermal conductivity gauge employs a carbon single-walled-nanotube. The gauge operates on the principle of thermal exchange between the voltage-biased nanotube and the surrounding gas at low levels of power and low temperatures to measure vacuum across a wide dynamic range. The gauge includes two terminals, a source of constant voltage to the terminals, a single-walled carbon nanotube between the terminals, a calibration of measured conductance of the nanotube to magnitudes of surrounding vacuum and a current meter in electrical communication with the source of constant voltage. Employment of the nanotube for measuring vacuum includes calibrating the electrical conductance of the nanotube to magnitudes of vacuum, exposing the nanotube to a vacuum, applying a constant voltage across the nanotube, measuring the electrical conductance of the nanotube in the vacuum with the constant voltage applied and converting the measured electrical conductance to the corresponding calibrated magnitude of vacuum using the calibration. The nanotube may be suspended to minimize heat dissipation through the substrate, increasing sensitivity at even tower pressures

Development of Thin Gold Film Thermal Sensors for Synchrotron X-Ray Exposure Diagnostics.

High aspect ratio lithography utilizes high intensity exposure sources, such as synchrotron storage rings, to deposit sufficient dose in the resist to produce a successful pattern transfer. Such highly powerful sources are known to cause undesirable thermal effects in the mask-resist-substrate system. Hence, the measurement of temperature of a mask-resist-substrate system during irradiation is an important exposure diagnostic feature. Deposition of a reasonably accurate dose in the resist is controlled by knowledge of the exposure source intensity. Periodic monitoring of the synchrotron radiation beam power and its spatial distribution at the exposure plane is necessary. In this research, diagnostic techniques based on thin gold film thermal sensors are developed to measure mask-resist-substrate temperature during exposure, and to measure the magnitude and spatial distribution of exposure radiation power. The suitability of thin gold film thermal sensors for exposure diagnostics are demonstrated. Fabrication, calibration and performance characteristics of these sensors are presented. Results of the temperature rise on the top surface of PMMA and at the interface of the Si-PMMA resist-substrate system in vacuum and at different pressures of helium are presented. Relaxation time parameter under different exposure ambiance is determined. The thermal sensor measurement is compared with that of conventional J-type miniature thermocouples, and temperature measurements are compared with results of a numerical simulation performed using the finite difference heat transfer code, HEATING. A calorimeter, based on the interlaced thermal sensors, has been developed to perform synchrotron radiation beam power measurements. The concept of internal calibration, that combines calibration and measurement into a single operation, is explained. The advantage of this technique in terms of the ambiance independent, calibration-free performance and fast response time is demonstrated in comparison with conventional calorimeters. A procedure, based on an integral type measurement to obtain the spatial power distribution in the beam is explained. The results of beam power measurement and beam profile measurement at the XRLC1 and the XRLM3 beamlines are presented. An empirical relationship between the synchrotron electron beam current and the synchrotron radiation power is developed to serve as a quick reference during exposures

Systems and Methods for Implementing Robust Carbon Nanotube-Based Field Emitters

Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate

Thermionic Power Cell To Harness Heat Energies for Geothermal Applications

A unit thermionic power cell (TPC) concept has been developed that converts natural heat found in high-temperature environments (460 to 700 C) into electrical power for in situ instruments and electronics. Thermionic emission of electrons occurs when an emitter filament is heated to gwhite hot h temperatures (>1,000 C) allowing electrons to overcome the potential barrier and emit into the vacuum. These electrons are then collected by an anode, and transported to the external circuit for energy storage

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus