A Simple Statutory Solution to Minority Oppression in the Closely-Held Business

Disputes involving closely held businesses come in primarily two varieties. When, as is often the case, the business fails, creditors bring lawsuits seeking to pierce the corporate veil in an attempt to reach the assets of the business owners. 3 When the business does well, on the other hand, minority owners often accuse those in control of seeking ways to keep a bigger slice of the profit pie and of squeezing or freezing out minority owners. 4 These latter disputes are often categorized under the rubric of minority shareholder oppression; and attempts to deal with them by statute and judicial decision are as old as corporate law. 5 Moreover, they are not unique to business in the United States; rather, they are part of the fabric of modern business organization law on a global scale

On-Line Monitoring for Temporal Logic Robustness

In this paper, we provide a Dynamic Programming algorithm for on-line monitoring of the state robustness of Metric Temporal Logic specifications with past time operators. We compute the robustness of MTL with unbounded past and bounded future temporal operators MTL over sampled traces of Cyber-Physical Systems. We implemented our tool in Matlab as a Simulink block that can be used in any Simulink model. We experimentally demonstrate that the overhead of the MTL robustness monitoring is acceptable for certain classes of practical specifications

Analog Property Checkers: A Ddr2 Case Study

The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach

Runtime Verification of Temporal Properties over Out-of-order Data Streams

We present a monitoring approach for verifying systems at runtime. Our approach targets systems whose components communicate with the monitors over unreliable channels, where messages can be delayed or lost. In contrast to prior works, whose property specification languages are limited to propositional temporal logics, our approach handles an extension of the real-time logic MTL with freeze quantifiers for reasoning about data values. We present its underlying theory based on a new three-valued semantics that is well suited to soundly and completely reason online about event streams in the presence of message delay or loss. We also evaluate our approach experimentally. Our prototype implementation processes hundreds of events per second in settings where messages are received out of order.Comment: long version of the CAV 2017 pape

Molecular biology of the apteronotus NMDA receptor NR1 subunit

The complete sequences and expression patterns of the NR1 (aptNR1) subunit of the N-methyl-d-aspartate (NMDA) receptor and its alternative splice isoforms have been determined for the weakly electric fish Apteronotus leptorhynchus. The deduced amino acid sequence of aptNR1 is approximately 88 % identical to the NR1 sequences of other vertebrate. Two of the three alternative splice cassettes previously described for mammalian NR1s, N1 and C1, are present in aptNR1, but the third cassette, C2, is not found. In addition, two teleost-specific splice cassettes occur on the N-terminal side of the C1 sequence. The cellular patterns of aptNR1 expression, including the patterns of N1 and C1 splicing, have been mapped using the in situ hybridization technique. High levels of aptNR1 mRNA were detected throughout the central nervous system including most neurons of the electrosensory system, with the highest levels in electrosensory lateral line lobe pyramidal cells. Expression of the N1 splice isoform was higher in more caudal regions of the brain, and expression of the C1 splice isoform was higher in more rostral regions. The N1 splice isoform was present in almost all NR1-positive cells, in contrast to the C1 splice isoform which was restricted to a subset of NR1-positive cells. These results demonstrate that the NR1 subunit of the NMDA receptor is evolutionarily conserved across species and that regulation of alternative RNA splicing modulates the properties of NR1 in different neurons of the central nervous system of A. leptorhynchus

Quantitative Regular Expressions for Arrhythmia Detection Algorithms

Motivated by the problem of verifying the correctness of arrhythmia-detection algorithms, we present a formalization of these algorithms in the language of Quantitative Regular Expressions. QREs are a flexible formal language for specifying complex numerical queries over data streams, with provable runtime and memory consumption guarantees. The medical-device algorithms of interest include peak detection (where a peak in a cardiac signal indicates a heartbeat) and various discriminators, each of which uses a feature of the cardiac signal to distinguish fatal from non-fatal arrhythmias. Expressing these algorithms' desired output in current temporal logics, and implementing them via monitor synthesis, is cumbersome, error-prone, computationally expensive, and sometimes infeasible. In contrast, we show that a range of peak detectors (in both the time and wavelet domains) and various discriminators at the heart of today's arrhythmia-detection devices are easily expressible in QREs. The fact that one formalism (QREs) is used to describe the desired end-to-end operation of an arrhythmia detector opens the way to formal analysis and rigorous testing of these detectors' correctness and performance. Such analysis could alleviate the regulatory burden on device developers when modifying their algorithms. The performance of the peak-detection QREs is demonstrated by running them on real patient data, on which they yield results on par with those provided by a cardiologist.Comment: CMSB 2017: 15th Conference on Computational Methods for Systems Biolog

Practical Automated Partial Verification of Multi-Paradigm Real-Time Models

This article introduces a fully automated verification technique that permits to analyze real-time systems described using a continuous notion of time and a mixture of operational (i.e., automata-based) and descriptive (i.e., logic-based) formalisms. The technique relies on the reduction, under reasonable assumptions, of the continuous-time verification problem to its discrete-time counterpart. This reconciles in a viable and effective way the dense/discrete and operational/descriptive dichotomies that are often encountered in practice when it comes to specifying and analyzing complex critical systems. The article investigates the applicability of the technique through a significant example centered on a communication protocol. More precisely, concurrent runs of the protocol are formalized by parallel instances of a Timed Automaton, while the synchronization rules between these instances are specified through Metric Temporal Logic formulas, thus creating a multi-paradigm model. Verification tests run on this model using a bounded validity checker implementing the technique show consistent results and interesting performances.Comment: 33 pages; fixed a few typos and added data to Table