13 research outputs found
3D nanowire gate-all-around transistors: Specific integration and electrical features
International audienc
Low-Temperature Transport Characteristics in SOI and sSOI Nanowires Down to 8nm Width: Evidence of Ids and Mobility Oscillations
International audienc
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs
International audienc
3D source/drain doping optimization in multi-channel MOSFET. ESSDERC
International audienc
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration.
National audienc
Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires
National audienc
Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width
International audienc
15nm-diameter 3D Stacked Nanowires with optional Independent Gates operation (?FET)
International audienc
Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects
Session 15: Nanowires (#15.3)International audienc