Measurements and tests on FBK silicon sensors with an optimized electronic design for a CTA camera

In October 2013, the Italian Ministry approved the funding of a Research & Development (R&D) study, within the "Progetto Premiale TElescopi CHErenkov made in Italy (TECHE)", devoted to the development of a demonstrator for a camera for the Cherenkov Telescope Array (CTA) consortium. The demonstrator consists of a sensor plane based on the Silicon Photomultiplier (SiPM) technology and on an electronics designed for signal sampling. Preliminary tests on a matrix of sensors produced by the Fondazione Bruno Kessler (FBK-Trento, Italy) and on electronic prototypes produced by SITAEL S.p.A. will be presented. In particular, we used different designs of the electronics in order to optimize the output signals in terms of tail cancellation. This is crucial for applications where a high background is expected, as for the CTA experiment.Comment: 5 pages, 6 figures; Proceedings of the 10th Workshop on Science with the New Generation of High-Energy Gamma-ray experiments (SciNeGHE) - PoS(Scineghe2014)00

Global Analysis of the Higgs Candidate with Mass ~ 125 GeV

We analyze the properties of the Higgs candidate with mass ~ 125 GeV discovered by the CMS and ATLAS Collaborations, constraining the possible deviations of its couplings from those of a Standard Model Higgs boson. The CMS, ATLAS and Tevatron data are compatible with Standard Model couplings to massive gauge bosons and fermions, and disfavour several types of composite Higgs models unless their couplings resemble those in the Standard Model. We show that the couplings of the Higgs candidate are consistent with a linear dependence on particle masses, scaled by the electroweak scale ~ 246 GeV, the power law and the mass scale both having uncertainties ~ 20%.Comment: 22 pages, 9 figures, v2 incorporates experimental data released during July 2012 and corrected (and improved) treatment of mass dependence of coupling

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Renormalisation group corrections to neutrino mixing sum rules

Neutrino mixing sum rules are common to a large class of models based on the (discrete) symmetry approach to lepton flavour. In this approach the neutrino mixing matrix $U$ is assumed to have an underlying approximate symmetry form \tildeU_\nu, which is dictated by, or associated with, the employed (discrete) symmetry. In such a setup the cosine of the Dirac CP-violating phase $\delta$ can be related to the three neutrino mixing angles in terms of a sum rule which depends on the symmetry form of \tildeU_\nu. We consider five extensively discussed possible symmetry forms of \tildeU_\nu: i) bimaximal (BM) and ii) tri-bimaximal (TBM) forms, the forms corresponding to iii) golden ratio type A (GRA) mixing, iv) golden ratio type B (GRB) mixing, and v) hexagonal (HG) mixing. For each of these forms we investigate the renormalisation group corrections to the sum rule predictions for $\delta$ in the cases of neutrino Majorana mass term generated by the Weinberg (dimension 5) operator added to i) the Standard Model, and ii) the minimal SUSY extension of the Standard Model

Predictions for the Leptonic Dirac CP Violation Phase: a Systematic Phenomenological Analysis

We derive predictions for the Dirac phase $\delta$ present in the $3\times 3$ unitary neutrino mixing matrix $U = U_e^{\dagger} \, U_{\nu}$, where $U_e$ and $U_{\nu}$ are $3\times 3$ unitary matrices which arise from the diagonalisation respectively of the charged lepton and the neutrino mass matrices. We consider forms of $U_e$ and $U_{\nu}$ allowing us to express $\delta$ as a function of three neutrino mixing angles, present in $U$, and the angles contained in $U_{\nu}$. We consider several forms of $U_{\nu}$ determined by, or associated with, symmetries, tri-bimaximal, bimaximal, etc., for which the angles in $U_{\nu}$ are fixed. For each of these forms and forms of $U_e$ allowing to reproduce the measured values of the neutrino mixing angles, we construct the likelihood function for $\cos \delta$, using i) the latest results of the global fit analysis of neutrino oscillation data, and ii) the prospective sensitivities on the neutrino mixing angles. Our results, in particular, confirm the conclusion reached in earlier similar studies that the measurement of the Dirac phase in the neutrino mixing matrix, together with an improvement of the precision on the mixing angles, can provide unique information about the possible existence of symmetry in the lepton sector

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Exploring holographic Composite Higgs models

Simple Composite Higgs models predict new vector-like fermions not too far from the electroweak scale, yet LHC limits are now sensitive to the TeV scale. Motivated by this tension, we explore the holographic dual of the minimal model, MCHM5, to try and alleviate this tension without increasing the fine-tuning in the Higgs potential. Interestingly, we find that lowering the UV cutoff in the 5D picture allows for heavier top partners and less fine-tuning. In the 4D dual this corresponds to increasing the number of “colours” N , thus increasing the decay constant of the Goldstone Higgs. This is essentially a ‘Little Randall-Sundrum Model’, which are known to reduce some flavour and electroweak constraints. Furthermore, in anticipation of the ongoing efforts at the LHC to put bounds on the top Yukawa, we demonstrate that deviations from the SM can be suppressed or enhanced with respect to what is expected from mere symmetry arguments in 4D. We conclude that the 5D holographic realisation of the MCHM5 with a small UV cutoff is not in tension with the current experimental data

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment