Sacra et Pretiosa - Oreficeria dai monasteri di Palermo Capitale

Si presenta il percorso della mostra articolata in due momenti Sacra et pretiosa. La prima parte, "Il monastero di Santa Caterina nel cuore di Palermo Capitale", ha valorizzato gli ambienti del monastero, facendoli rivivere attraverso la contestualizzazione di arredi originali ed opere d\u2019arte ancora esistenti e restituendo al loro contesto originario gli oggetti di uso quotidiano, le suppellettili liturgiche, gli arredi e le opere d\u2019arte che ne compongono lo straordinario patrimonio. La seconda Mostra, "Oreficeria dai monasteri di Palermo Capitale", propone una selezione di capolavori dell\u2019oreficeria siciliana realizzati tra XVI e XIX secolo, commissionati dagli ordini monastici nel contesto della citt\ue0It presents the path of the exhibition articulated in two moments Sacra et pretiosa. The first part, "The monastery of St. Catherine in the heart of Palermo Capital", has enhanced the rooms of the monastery, reviving them through the contextualization of original furnishings and works of art still existing and returning to their original context the objects of daily use, liturgical furnishings, furnishings and works of art that make up the extraordinary heritage. The second exhibition, "Goldsmithery from the monasteries of Palermo Capital", offers a selection of masterpieces of Sicilian goldsmithery made between the sixteenth and nineteenth centuries, commissioned by monastic orders in the context of the cit

Criteri di Museologia per il Museo Diocesano di Monreale

L'articolo espone i criteri museologici adottati nell'allestimento del Museo Diocesano di Monreale e a cui si \ue8 ispirato anche l'allestimento del Museo che conterr\ue0 le opere provenienti dall'abbazia di S. Maria del Bosco di Calatamauro sempre nel complesso del Duomo di Monreale, nel Dormitorio del convento prospiciente al chiostro in fase di realizzazione.The paper sets out the criteria adopted in museological setting of the Diocesan Museum of Monreale. They have also inspired the exhibition of the Museum, under construction, that will contain the works coming from the Abbey of Santa Maria del Bosco of Calatamauro. It will take place in the Dormitory of the Monastery overlooking the cloister, always in the complex of the Cathedral of Monreale

A programmable BIST architecture for clusters of Multiple-Port SRAMs

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC

This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft- error rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the So

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

Task Scheduling with RT Constraints

This paper addresses the problem of scheduling reactive realtime transactions (task groups) implementing a network of extended Finite State Machines communicating asynchronously. Task instances are..

Interactive Educational Tool for Memory Testing

Memories are one of the most important components in digital systems like SoCs. The high density of their cell array makes memories extremely vulnerable to physical defects. Hence, memory testing and Design-for-Test became one of the crucial tasks in the design of complex and heterogeneous SoCs. Politecnico di Torino and the Institute of Informatics have a wide experience in the field of RAM testing (i.e., automatic march test generation, fault simulators, memory BIST generators etc.). This work is a tentative to put the joint experience of our research groups in developing an interactive educational tool for the students that should introduce standard and well-known methods of memory testing based on BIST. The MemBIST Java Applet and the March Test Generator were two individual tools designed and implemented at the two mentioned institutions. They were merged into one tool in order to facilitate its usage also by the professional

Nazwy komitetów wyborczych – aspekty strukturalne i aksjologiczne

The subject of this paper will be a semantic and structural analysis of the names of electoral committees, and a reference to the axiological systems that are indirectly reflected by them. The names of electoral committees are obligatory elements of electoral activities, as well as being an interesting element of political marketing