Deep levels in silicon-oxygen superlattices

This work reports on the deep levels observed in Pt/Al2O3/p-type Si metal-oxide-semiconductor capacitors containing a silicon-oxygen superlattice (SL) by deep-level transient spectroscopy. It is shown that the presence of the SL gives rise to a broad band of hole traps occurring around the silicon mid gap, which is absent in reference samples with a silicon epitaxial layer. In addition, the density of states of the deep layers roughly scales with the number of SL periods for the as- deposited samples. Annealing in a forming gas atmosphere reduces the maximum concentration significantly, while the peak energy position shifts from close-to mid-gap towards the valence band edge. Based on the flat-band voltage shift of the Capacitance-Voltage characteristics it is inferred that positive charge is introduced by the oxygen atomic layers in the SL, indicating the donor nature of the underlying hole traps. In some cases, a minor peak associated with P-b dangling bond centers at the Si/SiO2 interface has been observed as well

Study of electrically active defects in epitaxial layers on silicon

Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at the substrate/epi layer interface. At the same time, a post-deposition Forming Gas Anneal can passivate to a large extent the active defect states. Finally, it is shown that application of a post-deposition anneal increases the out-diffusion of carbon from a Si:C stressor layer into the p-type CZ substrate

Electrical Characterization of Submicrometer Silicon Devices by Cross-Sectional Contact Mode Atomic Force Microscopy

Two contact mode atomic force microscopic (AFM) techniques under ambient conditions are presented for the electrical evaluation of cross sectioned silicon devices. In the first technique, a conductive AFM tip is used as a voltage probe to determine the local potential distribution on the cross section of a silicon device under operation. The electrical potential is measured simultaneously with the surface topography with nanometer resolution and mV accuracy, offering an easy way of correlating topographic and electrical features. A second method, nanometer spreading resistance profiling (nano-SRP), performs localized spreading resistance measurements to determine the spatial distribution of charge carriers in silicon structures. The conversion of the resistance profiles into charge carrier profiles as well as the applied correction factors are discussed in more detail. Both methods are used to map electrical characteristics of state-of-the-art silicon structures

Direct observation by resonant tunneling of the B^+ level in a delta-doped silicon barrier

We observe a resonance in the conductance of silicon tunneling devices with a delta-doped barrier. The position of the resonance indicates that it arises from tunneling through the B^+ state of the boron atoms of the delta-layer. Since the emitter Fermi level in our devices is a field-independent reference energy, we are able to directly observe the diamagnetic shift of the B^+ level. This is contrary to the situation in magneto-optical spectroscopy, where the shift is absorbed in the measured ionization energy.Comment: submitted to PR

Atomic layer deposition of high-k dielectric layers on Ge and III-V MOS channels

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied At. Layer Deposition (ALD) of high-k dielec. layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidn. in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidn. states lower than 4+. Still, elec. results indicate that small amts. of Ge in oxidn. states lower than 4+ are not detrimental for device performance. Partial intermixing was obsd. for high-k dielec. and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates. [on SciFinder (R)