Large scale graphene integration for silicon technologies

The main guarantor of success for silicon based semiconductor research and industry was the availability and continuous improve of wafer fabrication processes for large scale integration. New material integration in a stable and reliable silicon process platform has to face several challenges. Graphene as a 2D material is considered as a material with formidable properties. This can enable new functionalities and performance improvements in a large variety of applications. Using graphene devices in microelectronics requires beside appropriate performances certain techniques for large scale fabrication of graphene which are currently not yet in place. In this paper we present recent progress of process platform developments to enable wafer scale integration in a silicon cmos platform. Synthesis of graphene on silicon cmos compatible substrates are considered to fulfill a basic request for the integration of graphene related devices in a silicon environment with no risk of metallic cross contamination. We present recent results of graphene synthesis on Ge(100) and Ge (110). Therefore chemical vapor deposition (CVD) methods are used to realize Ge/Si substrates followed by a CVD graphene synthesis at ~890°C (1,2). Due to silicon diffusion inside germanium certain germanium thickness is required to allow the subsequent graphene process. We present high quality graphene on a 200mm silicon wafers with high uniformity, a 2D/G ratio of ~3 and low D mode over the entire 200mm wafer measured by Raman spectroscopy (Figure 1). To enable a selective graphene synthesis on a 200mm wafer we discuss first approaches of graphene growth on patterned germanium island. Please click Additional Files below to see the full abstract

Towards the Growth of Hexagonal Boron Nitride on Ge(001)/Si Substrates by Chemical Vapor Deposition

The growth of hexagonal boron nitride (hBN) on epitaxial Ge(001)/Si substrates via high-vacuum chemical vapor deposition from borazine is investigated for the first time in a systematic manner. The influences of the process pressure and growth temperature in the range of 10−7–10−3 mbar and 900–980 °C, respectively, are evaluated with respect to morphology, growth rate, and crystalline quality of the hBN films. At 900 °C, nanocrystalline hBN films with a lateral crystallite size of ~2–3 nm are obtained and confirmed by high-resolution transmission electron microscopy images. X-ray photoelectron spectroscopy confirms an atomic N:B ratio of 1 ± 0.1. A three-dimensional growth mode is observed by atomic force microscopy. Increasing the process pressure in the reactor mainly affects the growth rate, with only slight effects on crystalline quality and none on the principle growth mode. Growth of hBN at 980 °C increases the average crystallite size and leads to the formation of 3–10 well-oriented, vertically stacked layers of hBN on the Ge surface. Exploratory ab initio density functional theory simulations indicate that hBN edges are saturated by hydrogen, and it is proposed that partial de-saturation by H radicals produced on hot parts of the set-up is responsible for the growth

Electron Transport across Vertical Silicon/MoS2/Graphene Heterostructures: Towards Efficient Emitter Diodes for Graphene Base Hot Electron Transistors

Heterostructures comprising silicon, molybdenum disulfide (MoS2), and graphene are investigated with respect to the vertical current conduction mechanism. The measured current-voltage (I-V) characteristics exhibit temperature-dependent asymmetric current, indicating thermally activated charge carrier transport. The data are compared and fitted to a current transport model that confirms thermionic emission as the responsible transport mechanism across devices. Theoretical calculations in combination with the experimental data suggest that the heterojunction barrier from Si to MoS2 is linearly temperature-dependent for T = 200-300 K with a positive temperature coefficient. The temperature dependence may be attributed to a change in band gap difference between Si and MoS2, strain at the Si/MoS2 interface, or different electron effective masses in Si and MoS2, leading to a possible entropy change stemming from variation in density of states as electrons move from Si to MoS2. The low barrier formed between Si and MoS2 and the resultant thermionic emission demonstrated here make the present devices potential candidates as the emitter diode of graphene base hot electron transistors for future high-speed electronics. Copyright © 2020 American Chemical Society

Perfluorodecyltrichlorosilane-based seed-layer for improved chemical vapour deposition of ultrathin hafnium dioxide films on graphene

We investigate the use of perfluorodecyltrichlorosilane-based self-assembled monolayer as seeding layer for chemical vapour deposition of HfO2 on large area CVD graphene. The deposition and evolution of the FDTS-based seed layer is investigated by X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron microscopy. Crystalline quality of graphene transferred from Cu is monitored during formation of the seed layer as well as the HfO2 growth using Raman spectroscopy. We demonstrate that FDTS-based seed layer significantly improves nucleation of HfO2 layers so that graphene can be coated in a conformal way with HfO2 layers as thin as 10 nm. Proof-of-concept experiments on 200 mm wafers presented here validate applicability of the proposed approach to wafer scale graphene device fabrication

Electron Transport across Vertical Silicon/MoS2/Graphene Heterostructures: Towards Efficient Emitter Diodes for Graphene Base Hot Electron Transistors

Heterostructures comprising silicon, molybdenum disulfide (MoS2), and graphene are investigated with respect to the vertical current conduction mechanism. The measured current-voltage (I-V) characteristics exhibit temperature-dependent asymmetric current, indicating thermally activated charge carrier transport. The data are compared and fitted to a current transport model that confirms thermionic emission as the responsible transport mechanism across devices. Theoretical calculations in combination with the experimental data suggest that the heterojunction barrier from Si to MoS2 is linearly temperature-dependent for T = 200-300 K with a positive temperature coefficient. The temperature dependence may be attributed to a change in band gap difference between Si and MoS2, strain at the Si/MoS2 interface, or different electron effective masses in Si and MoS2, leading to a possible entropy change stemming from variation in density of states as electrons move from Si to MoS2. The low barrier formed between Si and MoS2 and the resultant thermionic emission demonstrated here make the present devices potential candidates as the emitter diode of graphene base hot electron transistors for future high-speed electronics. Copyright © 2020 American Chemical Society

Graphene growth on Ge(100)/Si(100) substrates by CVD method

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm−1

Deep reinforcement learning based optimization of automated guided vehicle time and energy consumption in a container terminal

The energy efficiency of port container terminal equipment and the reduction of CO2 emissions are among one of the biggest challenges facing every seaport in the world. The article pre sents the modeling of the container transportation process in a terminal from the quay crane to the stack using battery-powered Automated Guided Vehicle (AGV) to estimate the energy consump tion parameters. An AGV speed control algorithm based on Deep Reinforcement Learning (DRL) is proposed to optimize the energy consumption of container transportation. The results obtained and compared with real transportation measurements showed that the proposed DRL based approach dynamically changing the driving speed of the AGV reduces energy consumption by 4.6%. The obtained results of the research provide the prerequisites for further research in order to find optimal strategies for autonomous vehicle movement including context awareness and infor mation sharing with other vehicles in the terminal.Web of Science6740739