Ältere Migranten_innen im Stadtquartier

ÄLTERE MIGRANTEN_INNEN IM STADTQUARTIER Ältere Migranten_innen im Stadtquartier / Pantisano, Luigi (Rights reserved) ( -

EOT sub-nanométrico y degradación de la movilidad: ¿hacia un límite físico con las técnicas de fabricación modernas?

In this article we investigate the major problem of the micro/nano-electronic: How to redu­ce the Equivalent Oxide Thickness (EOT) in the sub-nanometric range and improving the MOSFET performance? To reduce the EOT it is necessary that the semiconductor indus­try introduce the high-K material as the Hafnium (Hf) in the dielectric layer. However the Hf produces a reduction of the mobility and therefore a reduction of the MOSFET speed. We explain through a simple semi-empirical model this mobility degradation in order to familiarize the reader with the concept of mobility for the high-K MOSFET. Afterward we focus on two optimized processing methods for the EOT reduction yielding the best gate stack quality. These processing methods are the Fully-Silicide (FuSi) gate with HfSiON dielectric and the Metal Gate with HfO2 which are both “gate first” based integration sche­me. The important results we found is that first we can obtain a sub-1nm EOT in the both cases although it was thought impossible to make it with high thermal budget process such as the FuSi method. Second, the mobility degradation is very similar in the both case in spite of the very different chemistries we use to form the gate stack. We conclude that the modern deposition technique does not allow controlling the dielectric quality as of 0.8 nm and we suggest using the “gate last” based integration scheme to improve further the gate stack quality.En este artículo investigamos un problema mayor de la microelectrónica moderna. Para reducir el EOT y aumentar el desempeño del MOSFET, la industria tiene que introducir el material high-K, como el Hf. Pero eso genera una degradación de la movilidad y una pérdida de la rapidez de los dispositivos. Explicamos esta degradación con un modelo muy sencillo para familiarizar al lector con el concepto de movilidad. Después nos enfocamos en dos procesamientos optimizados (Fully-Silicid con HfSiON y Metal Gate con HfO2) para reducir el EOT y causar un mínimo de defectos en el film. Un resultado muy impor­tante es que podemos lograr un EOT sub-nanométrico en los dos casos ya que esto fue considerado imposible con el FuSi/HfSiON. Otro resultado importante es que en los dos casos la degradación de la movilidad es muy parecida a pesar de que los dos procesamien­tos generan una pila de compuerta de naturaleza química muy diferente. Concluimos que con las técnicas de deposición moderna no se controla la calidad del dieléctrico a partir de 0.8 nm y sugerimos cambiar el esquema de integración con un “gate last”

Method for modulating the effective work function

EP1863072A1Published Applicatio

The Impact of Postbreakdown Gate Leakage on MOSFET RF Performances

Abstract—When the gate-oxide of a MOSFET breaks down, a leakage path is created between channel and gate. In this work, we demonstrate that a simple leakage current increase model can predict the impact of gate-oxide breakdown on MOSFET performance from dc to microwave frequency. We show that severe reduction in RF performance due to input/output mismatch and a gain reduction can result from gate-oxide breakdown. Index Terms—High frequency, MOSFET, oxide breakdown, reliability. I

Thermal recovery from stress-induced high-k dielectric film degradation

This work presents a detailed analysis of the ability of high-κ materials to recover from Fowler-Nordheim stress-induced degradation. Forming gas and high temperature rapid thermal anneal steps are compared to determine their efficiency at trap recovery. The annealing responses of the technologically relevant HfSiON and HfO₂ materials (equivalent oxide thickness <2 nm) are correlated with structural differences in these dielectrics, trap generation rate, charge centroids, and defect de-passivation. It is shown that stress-induced damage can be fully recovered for HfO₂ by high temperature annealing.status: publishe

Charge characterization in metal-gate/high-k layers: Effect of post-deposition annealing and gate electrode

The effect of varying interfacial SiO₂ and high-κ thickness on charge density within the gate stack are examined. It is demonstrated that there is a significant effect of the gate electrode on the charge density levels within the stack, with one order of magnitude lower charge in the case of Ni₃Si₂ electrodes, than in the case of tantalum-rich metal electrodes. The effect of post-deposition annealing on high-κ HfSiₓOy(Nz) stacks is less significant that that of the electrode. The reasons behind these findings are discussed.status: publishe

Effectiveness of nitridation of hafnium silicate dielectrics: A comparison between thermal and plasma nitridation

The results of a systematic study on the effects of nitrogen incorporation into (60%Hf/40%Si) hafnium silicate/SiO2 dielectric stacks are presented. Several nitridation methods and processes are compared as a function of the highest performing SiO2 interlayer/high-κ/post-deposition anneal combination on each wafer. It is shown that nitrogen incorporation results in a reduction in not only leakage current density but also maximum drive current, and carrier mobility. The relative increase in leakage current density with measurement temperature is independent of nitridation method or process, which indicates that phase separation may not be a problem for 2-nm hafnium silicate dielectrics. Depending on exact performance requirements, a nitridation step may not be necessary, as its benefits are limited (on ∼2.0 nm equivalent oxide thickness films) to a factor of 2 reduction in leakage current density, with 4% and 7% reduction in mobility and drive current, respectively.status: publishe

Performance assessment of (110) p-FET high-k/MG: is it mobility or series resistance limited?

In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the Ion at fixed Ioff is 100% larger for Si(110) larger than for standard Si(100). A thorough analysis of the factors influencing Ion (EOT, mobility and Rseries) for short channel devices (until Lmet= 80 nm) indicates that a 200% increase of the mobility at high Vg is the source of this performance enhancement. The lower Ion increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the Rseries (70% of the total resistance) for short channel devices. As a result additional room for Ion improvement can be reached by device and Rseries optimization.status: publishe