18 research outputs found
The Work of Roberto Busa SJ: Open Spaces between Computation and Hermeneutics
A review of the achievements of Fr. Busa over the course of his 60 years of work in the area of computational linguistics: internal hypertexts, the systematization of allographs, lemmatization, homographs and typologies; the lexical system; the laws of
economy for graphemes, for semantic typology, for heterogeneity among terms, and of the two lexical hemispheres. Finally, the project of disciplined languages is mentioned, a response to the linguistic challenge resulting from informational globalization
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
We propose two tiers of modifications to FPGA logic cell architecture to
deliver a variety of performance and utilization benefits with only minor area
overheads. In the irst tier, we augment existing commercial logic cell
datapaths with a 6-input XOR gate in order to improve the expressiveness of
each element, while maintaining backward compatibility. This new architecture
is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary
tier of vendor-speciic modifications to both Xilinx and Intel FPGAs, which we
refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor
tree synthesis using generalized parallel counters (GPCs) is further improved
with the proposed modifications. Using both the Intel adaptive logic module and
the Xilinx slice at the 65nm technology node for a comparative study, it is
shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for
LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We
demonstrate that LUXOR can deliver an average reduction of 13-19% in logic
utilization on micro-benchmarks from a variety of domains.BNN benchmarks
benefit the most with an average reduction of 37-47% in logic utilization,
which is due to the highly-efficient mapping of the XnorPopcount operation on
our proposed LUXOR+ logic cells.Comment: In Proceedings of the 2020 ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays (FPGA'20), February 23-25, 2020, Seaside, CA,
US
A Memory Unit for Priority Management in IPSec Accelerators
Abstract — This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed. I
A serial-input serial-output bit-sliced convolver
A novel convolver is presented in which both samples and results are in serial form, while coefficients are stored in internal registers. The convolver is composed of an array of multiplier-accumulator subunits which operate in a carry-save, serial/parallel mode. The sample bits are broadcast to all subunits, each one executing the multiplication with the stored coefficient and accumulating the product with the result received from the preceding unit. The structure can be shown to be decomposable in bit-slices; a stack of slices can be programmed as a convolver for prescribed sample and coefficient bit-length under the control of a configuration register. Faulty slices can be neutralized by variables stored in a second register
Bit-serial fault-tolerant architectures for convolution and polynomial evaluation
The authors present three distinct serial-input serial-output architectures: two for the computation of discrete convolution (bit-sliced and polyphase convolvers) and one for polynomial evaluation (polynomiers). These devices operate in serial fixed point natural arithmetic. All architectures are characterized by a bit-sliced structure that makes possible easy design and testing. The regular, uniform bit-slices also give the possibility of introducing functional reconfigurability and fault tolerance. For all these reasons, the proposed three architectures are good candidates for VLSI and WSI (wafer scale integration) implementation. Prototypal layouts, testing procedures, and statistical analysis have been developed for the evaluation of the architecture performances, the introduction of fault tolerance, and the study of the obtained fault coverage, reliability, and fabrication yield