IDeF-X ASIC for Cd(Zn)Te spectro-imaging systems

Joint progresses in Cd(Zn)Te detectors, microelectronics and interconnection technologies open the way for a new generation of instruments for physics and astrophysics applications in the energy range from 1 to 1000 keV. Even working between -20 and 20 degrees Celsius, these instruments will offer high spatial resolution (pixel size ranging from 300 x 300 square micrometers to few square millimeters), high spectral response and high detection efficiency. To reach these goals, reliable, highly integrated, low noise and low power consumption electronics is mandatory. Our group is currently developing a new ASIC detector front-end named IDeF-X, for modular spectro-imaging system based on the use of Cd(Zn)Te detectors. We present here the first version of IDeF-X which consists in a set of ten low noise charge sensitive preamplifiers (CSA). It has been processed with the standard AMS 0.35 micrometer CMOS technology. The CSA are designed to be DC coupled to detectors having a low dark current at room temperature. The various preamps implemented are optimized for detector capacitances ranging from 0.5 up to 30 pF.Comment: 8 pages, 11 figures, IEEE NSS-MIC conference in Rome 2004, submitted to IEEE TNS, correction in unit of figure

A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock

During the last decade, ADCs using single ramp architecture have been widely used in integrated circuits dedicated to nuclear science applications. These types of converters are actually very well suited for low power, multi-channel applications. Moreover their wide dynamic range and their very good differential non-linearity are perfectly matched to spectroscopy measurement. Unfortunately, their use is limited by their long conversion time, itself limited by their maximum clock frequency. A new architecture is described in this paper. It permits speeding up the conversion time of the traditional ramp ADC structures by a factor of 32 while keeping a low power consumption. Measurement results on a 4-channel, 12-bit prototype using a 3.2 GHz virtual clock are then presented in detail, showing excellent performances of linearity and noise

CARET analysis of multithreaded programs

Dynamic Pushdown Networks (DPNs) are a natural model for multithreaded programs with (recursive) procedure calls and thread creation. On the other hand, CARET is a temporal logic that allows to write linear temporal formulas while taking into account the matching between calls and returns. We consider in this paper the model-checking problem of DPNs against CARET formulas. We show that this problem can be effectively solved by a reduction to the emptiness problem of B\"uchi Dynamic Pushdown Systems. We then show that CARET model checking is also decidable for DPNs communicating with locks. Our results can, in particular, be used for the detection of concurrent malware.Comment: Pre-proceedings paper presented at the 27th International Symposium on Logic-Based Program Synthesis and Transformation (LOPSTR 2017), Namur, Belgium, 10-12 October 2017 (arXiv:1708.07854

SCTA - A Rad-Hard BiCMOS Analogue Readout ASIC for the ATLAS Semiconductor Tracker

Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channels and 128 channel versions, using the radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 ms and 2.5 ms. The chip has been tested successfully and subsequently irradiated up to 10 Mrad. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC = 720 e- + 33 e-/pF before irradiation and 840 e- + 33 e-/pF after irradiation have been obtained

MATE, a single front-end ASIC for silicon strip, Si(Li) and CsI detectors

MATE (Must ASIC for Time and Energy) will process signals delivered from the hodoscope MUST2. The hodoscope consists of six large area telescopes (100 cm²), each made up of a double sided Si strip detector followed by a Si(Li) and Csi crystal. MATE has sixteen channels and can deliver three types of analogue information per channel; time of flight and energy loss of the detected particle; value of leakage DC current per channel. MATE also gives a trigger logical signal corresponding to the cross over of an adjustable threshold value. The analogue information is transmitted as differential current through twisted pair to the acquisition system based on VXI-C. The slow control is assured via the I2C industrial protocol. The first version of MATE for Si(strip) is available. An update of MATE will allow it to be used for the Si(Li) and Csi detectors. MATE is a novel R&D project for nuclear physics which includes both energy and time measurements with good resolution and high energy dynamic range

Development of a modular CdTe detector plane for gamma-ray burst detection below 100 keV

We report on the development of an innovative CdTe detector plane (DPIX) optimized for the detection and localization of gamma-ray bursts in the X-ray band (below 100 keV). DPIX is part of an R&D program funded by the French Space Agency (CNES). DPIX builds upon the heritage of the ISGRI instrument, currently operating with great success on the ESA INTEGRAL mission. DPIX is an assembly of 200 elementary modules (XRDPIX) equipped with 32 CdTe Schottky detectors (4x4 mm2, 1 mm thickness) produced by ACRORAD Co. LTD. in Japan. These detectors offer good energy response up to 100 keV. Each XRDPIX is readout by the very low noise front-end electronics chip IDeF-X, currently under development at CEA/DSM/DAPNIA. In this paper, we describe the design of XRDPIX, the main features of the IDeF-X chip, and will present preliminary results of the reading out of one CdTe Schottky detector by the IDeF-X V1.0 chip. A low-energy threshold around 2.7 keV has been measured. This is to be compared with the 12-15 keV threshold of the ISGRI-INTEGRAL and BAT-SWIFT instruments, which both use similar detector material.Comment: 5 pages, 4 figures in color, Advances in Space Research, COSPAR meeting, Beijing (2006

Constrained Dynamic Tree Networks

We generalise Constrained Dynamic Pushdown Networks, introduced by Bouajjani\et al, to Constrained Dynamic Tree Networks.<br>In this model, we have trees of processes which may monitor their children.<br>We allow the processes to be defined by any computation model for which the alternating reachability problem is decidable.<br>We address the problem of symbolic reachability analysis for this model. More precisely, we consider the problem of computing an effective representation of their reachability<br>sets using finite state automata. <div>We show that backwards reachability sets starting from regular sets of configurations are always regular. </div><div>We provide an algorithm for computing backwards reachability sets using tree automata.<br><br></div