Modeling heat transfer in dilute two-phase flows using the Mesoscopic Eulerian Formalism

In dilute two-phase flows, accurate prediction of the temperature of the dis- persed phase can be of paramount importance. Indeed, processes such as evaporation or chemical reactions are strongly non-linear functions of heat transfer between the carrier and dispersed phases. This study is devoted to the validation of an Eulerian description of the dispersed phase –the Meso- scopic Eulerian Formalism (MEF)– in the case of non-isothermal flows. Di- rect numerical simulations using the MEF are compared to a reference La- grangian simulation for a two-dimensional non-isothermal turbulent jet laden with solid particles. The objectives of this paper are (1) to study the influ- ence of the thermal inertia of particles on their temperature distribution and (2) conduct an a posteriori validation of the MEF, which was recently ex- tended to non-isothermal flows. The focus is on the influence of additional terms in the MEF governing equations, namely heat fluxes arising from the Random Uncorrelated Motion (RUM). Results show that mean and rms of particle temperature are strongly dependent of the thermal Stokes number. The mean temperature is satisfactorily predicted by the MEF, comparing to the Lagrangian reference. Under the conditions of the present study, the RUM heat fluxes have a marginal influence on the mean particle tempera- ture. However, a significant impact was observed on the magnitude of particle temperature fluctuations. Neglecting the RUM heat fluxes leads to erroneous results while the Lagrangian statistics are recovered when it is accounted for in the regimes of low to moderate thermal Stokes number

Si(100)-SiO2 interface properties following rapid thermal processing

An experimental examination of the properties of the Si(100)-SiO2 interface measured following rapid thermal processing (RTP) is presented. The interface properties have been examined using high frequency and quasi-static capacitance-voltage (CV) analysis of metal-oxide-silicon (MOS) capacitor structures immediately following either rapid thermal oxidation (RTO) or rapid thermal annealing (RTA). The experimental results reveal a characteristic peak in the CV response measured following dry RTO and RTA (T > 800 degreesC), as the Fermi level at the Si(100)-SiO2 interface approaches the conduction band edge. Analysis of the QSCV responses reveals a high interface state density across the energy gap following dry RTO and RTA processing, with a characteristic peak density in the range 5.5x10(12) to 1.7x10(13) cm(-2) eV(-1) located at approximately 0.85-0.88 eV above the valence band edge. When the background density of states for a hydrogen-passivated interface is subtracted, another peak of lower density (3x10(12) to 7x10(12) cm(-2) eV(-1)) is observed at approximately 0.25-0.33 eV above the valence band edge. The experimental results point to a common interface state defect present after processes involving rapid cooling (10(1)-10(2) degreesC/s) from a temperature of 800 degreesC or above, in a hydrogen free ambient. This work demonstrates that the interface states measured following RTP (T > 800 degreesC) are the net contribution of the P-b0/P-b1 silicon dangling bond defects for the oxidized Si(100) orientation. An important conclusion arising from this work is that the primary effect of an RTA in nitrogen (600-1050 degreesC) is to cause hydrogen desorption from pre-existing P-b0/P-b1 silicon dangling bond defects. The implications of this work to the study of the Si-SiO2 interface, and the technological implications for silicon based MOS processes, are briefly discussed. The significance of these new results to thin oxide growth and optimization by RTO are also considered

Approximate computing design exploration through data lifetime metrics

When designing an approximate computing system, the selection of the resources to modify is key. It is important that the error introduced in the system remains reasonable, but the size of the design exploration space can make this extremely difficult. In this paper, we propose to exploit a new metric for this selection: data lifetime. The concept comes from the field of reliability, where it can guide selective hardening: the more often a resource handles "live" data, the more critical it be-comes, the more important it will be to protect it. In this paper, we propose to use this same metric in a new way: identify the less critical resources as approximation targets in order to minimize the impact on the global system behavior and there-fore decrease the impact of approximation while increasing gains on other criteria

Towards a Secure and Reliable System

Abstract. In this article we describe a system based on a 32-bit processor, Leon, complete with security features offered by a specific cryptographic AES IP. Hardening is done not only on the principal hardware components but on the operating system as well, with attention for possible interaction between the different levels. The cryptographic IP is protected too to offer good resistance against, for example, fault-based attacks

Méthodologie d'évaluation de la sensibilité des microprocesseurs vis à vis des rayonnements cosmiques.

Les circuits électroniques embarqués dans les systèmes évoluant au niveau spatial ou dans l atmosphère sont soumis à des particules naturellement présentes qui peuvent provoquer une perturbation de leur fonctionnement. Le type d effet lié à ces particules le plus souvent rencontré dans les composants logiques est le SEU. Cet effet correspond à l inversion de l état logique d un élément de mémorisation. De nombreuses études ont été menées pour mettre au point des outils et méthodologies permettant de caractériser la sensibilité des mémoires (SRAM principalement) vis-à-vis de ce type d effets. Néanmoins, avec l augmentation importante de l électronique embarquée et plus particulièrement, l utilisation de composants de plus en plus complexes comme les microprocesseurs multicoeurs, il est devenu difficile, à l aide des outils jusque là disponibles, de déterminer l impact réel d une erreur déclenchée dans un élément de mémorisation sur une application exécutée par le système électronique. L utilisation des outils et méthodologies actuellement disponibles ne constituent alors qu'une approche pire cas : tous les éléments de mémorisation non protégés du composant sont comptabilisés et considérés comme sensibles, ce qui amène à considérer des marges importantes lors de l'analyse de risque de l'équipement. Une réduction importante de ces marges est possible en analysant le comportement dynamique de l'application opérée par le composant complexe. En effet, tous les éléments de mémorisation ne sont pas sensibles 100% du temps et de nombreux mécanismes de masquage peuvent faire en sorte qu'une erreur au niveau composant n'ait pas d'incidence sur l'application. Ce sujet de thèse aboutira à la mise au point d'un outil permettant de connaitre avec plus de précisions la sensibilité réelle d'une application opérée sur un microprocesseur, en vue d'optimiser les protections nécessaires et plus particulièrement, de tirer profit de l architecture spécifique des microprocesseurs multicoeurs. Pour réaliser cette étude, les axes suivants seront investigués : - Étude de l architecture des microprocesseurs - Utilisation des modèles de performance de processeurs - Utilisation des techniques d émulation par FPGA - Analyse logicielle du code de l application Des validations expérimentales sous laser et faisceau de particules seront également réalisées.The electronic circuits embarked on the systems evolving in the spatial level or in the atmosphere are subjected(submitted) to naturally present particles which can cause(provoke) a disturbance of their functioning. The type(chap) of effect bound(connected) to these particles most of the time met in the logical components is the SEU. This effect corresponds to the inversion of the logical state of an element of memorization. Numerous studies were led to finalize(to work out) tools and methodologies allowing to characterize the sensibility of reports(memoirs) (SRAM mainly) towards this type(chap) of effects. Nevertheless, with the important increase of the embarked electronics and more particularly, the use of more and more complex components as microprocessors multihearts, he(it) becameSAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes

Cette thèse s'intéresse en premier lieu à l'évaluation des effets fonctionnels des erreurs survenant dans la mémoire SRAM de configuration de certains FPGAs. La famille Virtex II Pro de Xilinx est utilisée comme premier cas pratique d'expérimentation. Des expérimentations sous faisceau laser nous ont permis d'avoir une bonne vue d'ensemble sur les motifs d'erreurs réalistes qui sont obtenus par des sources de perturbations réelles. Une méthodologie adaptée d'injection de fautes a donc été définie pour permettre une meilleure évaluation, en phase de conception, de la robustesse d'un circuit implanté sur ce type de technologie. Cette méthodologie est basée sur de la reconfiguration dynamique. Le même type d'approche a ensuite été évalué sur plusieurs cibles technologiques, ce qui a nécessité le développement de plusieurs environnements d'injection de fautes. L'étude a pour la première fois inclus la famille AT40K de ATMEL, qui permet un type de reconfiguration unique et efficace. Le second type de contribution concerne l'augmentation à faible coût de la robustesse de circuits implantés sur des plateformes FPGA SRAM. Nous proposons une approche de protection sélective exploitant les ressources du FPGA inutilisées par l'application. L'approche a été automatisée sur plusieurs cibles technologiques (Xilinx, Altera) et l'efficacité est analysée en utilisant les méthodes d'injection de fautes précédemment développées.This thesis focuses primarily on the evaluation of the functional effects of errors occurring in the SRAM configuration memory of some FPGAs. Xilinx Virtex II Pro family is used as a first case study. Experiments under laser beam allowed us to have a good overview of realistic error patterns, related to real disturbance sources. A suited fault injection methodology has thus been defined to improve design-time robustness evaluations of a circuit implemented on this type of technology. This methodology is based on runtime reconfiguration. The approach has then been evaluated on several technological targets, requiring the development of several fault injection environments. The study included for the first time the ATMEL AT40K family, with a unique and efficient reconfiguration mode. The second type of contribution is focused on the improvement at low cost of the robustness of designs implemented on SRAM-based FPGA platforms. We propose a selective protection approach exploiting resources unused by the application. The approach has been automated on several technological targets (Xilinx, Altera) and the efficiency has been analyzed by taking advantage of the fault injection techniques previously developed.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic

International audienceHigh-Level Synthesis (HLS) is used by hardware developers to achieve higher abstraction in circuit descriptions. In order to shorten the hardware development time via HLS, we present an adjustment of the Iterative and Incremental Design (IID) methodology, frequently used in software development. In particular, our methodology is relevant for the development of applications with unusual complexity: the method was applied here to the development of large modular arithmetic, commonly used for cryptography applications (e.g., Elliptic Curves). Rapid feedback on circuit characteristics is used to evaluate deep architectural changes in short time, greatly reducing the time-to-market with respect to hand-made designs. In addition, our approach is highly flexible, since the same generic high-level description can be used to produce an entire set of circuits, each with different area/performance trade-offs. Thanks to the proposed approach, any change to the initial specification (e.g., the curve used) is also very fast, while it may require a large effort in the case of hand-made designs

Simulation DNS de l'interaction flamme-paroi dans les moteurs à allumage commandé

Dans le cadre du projet INTERMARC (INTERaction dans les Moteurs à Allumage Commandé), la tâche du CORIA a consisté à produire une base de données à l'échelle RANS (provenant de données DNS) afin de tester, valider et modifier le modèle d'interaction développée par IFPen. Ce modèle vise l'ajout d'une composante d'interaction, phénomène non pris en compte par les lois de paroi actuelles.Ce projet repose sur l'interaction forte entre les différents protagonistes présents. Le CORIA et le CETHIL ont travaillé ensemble à la réalisation d'une base de données pour tester les modèles initiaux proposés par IFPen, puis en fonction des résultats obtenus, à itérer avec IFPen pour modifier et améliorer les modèles. Ces tests ont inclus des simulations 2D laminaires, 2D turbulentes, et 3D turbulentes.Under the INTERMARC project (Flame wall interaction in spark ignition engines), CORIA's job was to produce a database to RANS scale (from DNS data) to test, validate and modify the interaction model developed by IFPEN. This model aims the addition of the interaction phenomena, non-captured by the current wall laws. This project is based on the strong interaction between the different actors. The CORIA and the CETHIL have worked together in the creation of the database, where the experimental data were also used to validate the resuslts of the DNS code.CORIA then used this database to test the original model proposed by IFPPEN, then according to the resuslts obtained, CORIA iterated with IFPEN to modify and improve the models. These tests included laminar 2D simulations, 2D turbulent and 3D turbulent simulations.ROUEN-INSA Madrillet (765752301) / SudocSudocFranceF

Do grain boundaries in nanophase metals slide?

Nanophase metallic materials show a maximum in strength as grain size decreases to the nano scale, indicating a break down of the Hall-Petch relation. Grain boundary sliding, as a possible accommodation mechanisms, is often the picture that explain computer simulations results and real experiments. In a recent paper, Bringa et al. Science 309, 1838 (2005), we report on the observation of an ultra-hard behavior in nanophase Cu under shock loading, explained in terms of a reduction of grain boundary sliding under the influence of the shock pressure. In this work we perform a detailed study of the effects of hydrostatic pressure on nanophase Cu plasticity and find that it can be understood in terms of pressure dependent grain boundary sliding controlled by a Mohr-Coulomb law