Electroplated Ni mask for plasma etching of submicron-sized features in LiNbO3

International audienceWe here report on the fabrication of electroplated nickel (Ni) masks for dry etching of sub-micron patterns in lithium niobate (LiNbO3). This process allows obtaining 350-nm thick Ni masks defining high air filling fraction holey arrays (e.g. openings of 1800 nm in diameter with inter-hole spacing of 300 nm, or 330 nm diameter holes spaced by 440 nm). The mask profile is perfectly vertical (angle ≈ 90°). The obtained metallic masks are used to realise photonic and phononic crystals. High aspect ratio and dense arrays of holey patterns were defined and transferred into LiNbO3 through RIE (Reactive Ionic Etching) in sulphur hexafluoride (SF6) chemistry. Nanometric holes exhibiting sidewall slope angles of the order of 60° have in this way been etched in LiNbO3. The LiNbO3/Ni selectivity is close to 6 and the etch rate around 6 nm/min

Synthesis and characterization of crystalline silicon blades by VLS growth for sequential 3D integration of MOS transistors

L’intégration en trois dimensions se présente comme une alternative à la réduction des dimensions pour poursuivre l’augmentation continuelle de la densité des composants. Elle permet également de réduire le délai dans les interconnexions. Un autre avantage, non négligeable, est la possibilité d’ajouter de nouvelles fonctionnalités sur les niveaux supérieurs. Cependant, l’empilement de composants et leur interconnexion verticale doivent faire face à deux difficultés majeures. Tout d’abord, l’obtention d’un substrat semi-conducteur monocristallin de haute qualité sur une couche diélectrique doit s’effectuer sans détériorer les composants réalisés précédemment, en respectant une température limite. Ensuite, les composants supérieurs doivent être alignés avec précision par rapport au niveau inférieur, et doivent être intégrés tout en respectant le budget thermique imposé par les transistors déjà existants.Dans ce contexte, cette thèse s’attache à démontrer une approche innovante pour la synthèse de la couche active supérieure, en utilisant la croissance par CVD catalytique (VLS) confinée et guidée à l’intérieur d’une cavité. Ce manuscrit est composé de 4 chapitres : Le premier chapitre rappelle les notions de base des dispositifs et technologies MOS et fournit une analyse des différentes sources de dégradation liées à la miniaturisation. L’intégration en trois dimensions est ensuite introduite, accompagnée des différents procédés de fabrication. Une autre méthode de synthèse de silicium monocristallin plus originale est proposée : la croissance VLS. Le deuxième chapitre est consacré à la croissance VLS de nanofils de silicium sur substrat amorphe. L’aspect théorique et l’optimisation de la recette de croissance sont détaillés. Ainsi, des nanofils de silicium rectilignes avec des diamètres et des positions parfaitement contrôlés sont obtenus grâce à des motifs catalytiques définis par lift-off. Dans le troisième chapitre, une méthode de fabrication de cavité compatible avec l’approche 3D est proposée afin de contrôler avec précision les dimensions et la position du silicium formée par VLS. Une étude de la croissance de nanolames par VLS confinée dans ces cavités est proposée. Deux techniques de caractérisation structurale complémentaires (EBSD, STEM) sont utilisées afin d’analyser en détail la structure du silicium. Le dernier chapitre présente la fabrication de transistors MOS en utilisant les lames de silicium produites par VLS comme canal de conduction. L’intégration de transistors à grille arrière nous a permis de déterminer les paramètres élémentaires du transport et de les comparer à ceux des substrats SOI commerciaux.Three-dimensional integration of semiconductor devices is perceived as an alternative to device scaling in order to continue the increasing of the devices density. Moreover, it can reduce interconnect delay. Finally it allows the addition of different technologies in the back-end of the line, therefore enabling more applications. 3D integration requires the stacking of active layers alternated with interlayer dielectrics (ILD). The first challenge consists in growing crystal quality semiconductor starting on an amorphous substrate. The second difficulty concerns the device integration: the alignment registration between several active layers must be accurate and the temperature of fabrication is limited by the silicidation thermal budget of transistors integrated in inferior layers. In this context, this thesis demonstrates the synthesis of the crystalline silicon active layers using a new method, namely, the catalytic confined and guided Vapor-Liquid-Solid (VLS) growth.This manuscript is organized into four chapters: The first chapter develops fundamental notions associated to MOS devices and technologies, and provides an analysis of parasitic effects due to miniaturization. Three-dimensional integration is subsequently introduced with a detailed discussion on fabrication process. A new method is proposed to grow crystal semiconductor on an amorphous layer: the VLS growth. The second chapter is devoted to the VLS growth of silicon nanowires on an amorphous substrate. The theoretical aspect and the recipe optimization are developed. The localization of nanowires is controlled by catalyst patterns made by lift-off. In the third chapter, one method of cavity fabrication is proposed in order to control with accuracy dimensions and position of silicon blade synthetized by VLS. The single crystalline nature of silicon has been checked based on complementary techniques: Electron Back-Scattered Diffraction (EBSD) and Scanning Transmission Electron Microscopy (STEM). The last chapter presents the electrical characterization of VLS grown silicon nanoribbons. For that sake, “pseudo-MOS” transistors have been fabricated using VLS grown silicon blade as conduction channel and back-gate control. The characteristics of these transistors were extracted and compared to that of commercial SOI thin films

Jouvence et évolutions du bâti "TEGAL 915"

Ce rapport technique détaille la jouvence d'un bâti de gravure plasma "TEGAL 915" utilisé dans la centrale de technologie du LAAS-CNRS

Jouvence et évolutions du bâti "TEGAL 915"

Ce rapport technique détaille la jouvence d'un bâti de gravure plasma "TEGAL 915" utilisé dans la centrale de technologie du LAAS-CNRS

Synthèse et caractérisation de silicium cristallin par croissance VLS pour l'intégration 3D séquentielle de transistors MOS

L intégration en trois dimensions se présente comme une alternative à la réduction des dimensions pour poursuivre l augmentation continuelle de la densité des composants. Elle permet également de réduire le délai dans les interconnexions. Un autre avantage, non négligeable, est la possibilité d ajouter de nouvelles fonctionnalités sur les niveaux supérieurs. Cependant, l empilement de composants et leur interconnexion verticale doivent faire face à deux difficultés majeures. Tout d abord, l obtention d un substrat semi-conducteur monocristallin de haute qualité sur une couche diélectrique doit s effectuer sans détériorer les composants réalisés précédemment, en respectant une température limite. Ensuite, les composants supérieurs doivent être alignés avec précision par rapport au niveau inférieur, et doivent être intégrés tout en respectant le budget thermique imposé par les transistors déjà existants.Dans ce contexte, cette thèse s attache à démontrer une approche innovante pour la synthèse de la couche active supérieure, en utilisant la croissance par CVD catalytique (VLS) confinée et guidée à l intérieur d une cavité. Ce manuscrit est composé de 4 chapitres : Le premier chapitre rappelle les notions de base des dispositifs et technologies MOS et fournit une analyse des différentes sources de dégradation liées à la miniaturisation. L intégration en trois dimensions est ensuite introduite, accompagnée des différents procédés de fabrication. Une autre méthode de synthèse de silicium monocristallin plus originale est proposée : la croissance VLS. Le deuxième chapitre est consacré à la croissance VLS de nanofils de silicium sur substrat amorphe. L aspect théorique et l optimisation de la recette de croissance sont détaillés. Ainsi, des nanofils de silicium rectilignes avec des diamètres et des positions parfaitement contrôlés sont obtenus grâce à des motifs catalytiques définis par lift-off. Dans le troisième chapitre, une méthode de fabrication de cavité compatible avec l approche 3D est proposée afin de contrôler avec précision les dimensions et la position du silicium formée par VLS. Une étude de la croissance de nanolames par VLS confinée dans ces cavités est proposée. Deux techniques de caractérisation structurale complémentaires (EBSD, STEM) sont utilisées afin d analyser en détail la structure du silicium. Le dernier chapitre présente la fabrication de transistors MOS en utilisant les lames de silicium produites par VLS comme canal de conduction. L intégration de transistors à grille arrière nous a permis de déterminer les paramètres élémentaires du transport et de les comparer à ceux des substrats SOI commerciaux.Three-dimensional integration of semiconductor devices is perceived as an alternative to device scaling in order to continue the increasing of the devices density. Moreover, it can reduce interconnect delay. Finally it allows the addition of different technologies in the back-end of the line, therefore enabling more applications. 3D integration requires the stacking of active layers alternated with interlayer dielectrics (ILD). The first challenge consists in growing crystal quality semiconductor starting on an amorphous substrate. The second difficulty concerns the device integration: the alignment registration between several active layers must be accurate and the temperature of fabrication is limited by the silicidation thermal budget of transistors integrated in inferior layers. In this context, this thesis demonstrates the synthesis of the crystalline silicon active layers using a new method, namely, the catalytic confined and guided Vapor-Liquid-Solid (VLS) growth.This manuscript is organized into four chapters: The first chapter develops fundamental notions associated to MOS devices and technologies, and provides an analysis of parasitic effects due to miniaturization. Three-dimensional integration is subsequently introduced with a detailed discussion on fabrication process. A new method is proposed to grow crystal semiconductor on an amorphous layer: the VLS growth. The second chapter is devoted to the VLS growth of silicon nanowires on an amorphous substrate. The theoretical aspect and the recipe optimization are developed. The localization of nanowires is controlled by catalyst patterns made by lift-off. In the third chapter, one method of cavity fabrication is proposed in order to control with accuracy dimensions and position of silicon blade synthetized by VLS. The single crystalline nature of silicon has been checked based on complementary techniques: Electron Back-Scattered Diffraction (EBSD) and Scanning Transmission Electron Microscopy (STEM). The last chapter presents the electrical characterization of VLS grown silicon nanoribbons. For that sake, pseudo-MOS transistors have been fabricated using VLS grown silicon blade as conduction channel and back-gate control. The characteristics of these transistors were extracted and compared to that of commercial SOI thin films.LILLE1-Bib. Electronique (590099901) / SudocSudocFranceF

Miniaturized 3D gas sensors based on silicon nanowires for ppb range detection

International audienceThe atmosphere is a complex natural gaseous system that is essential to support life. Stratospheric ozone depletion due to air pollution has been recognized as a threat to human health as well as to the ecosystems. Some of the most prominent gaseous air pollutants are SOx, NOx, CO, NH3 and VOCs, all mainly produced by human activity. Moreover the ability to monitoring the air quality is essential to prevent health effects. Regarding the NO2, which reacts with the intern mucus membrane of lungs, and produces nitric acid, the recommended long period exposure is below the olfactory level (300ppb). Most commercial sensors, using metal oxide as sensitive layer, have two drawbacks: sensitivity in the ppm range and global power consumption. One-dimensional nanostructures, such as nanowires, hold a great potential for the new generation of high sensitive sensors, nevertheless very few demonstrations showed sub-50 ppb sensitivity. Here, we report 3D devices based on silicon nanowires (SiNW) for chemical gas sensing, working at room temperature. This sensor combines for the first time high sensibility, selectivity, reversibility, low-power consumption, reliability and low-cost large scale fabrication. Under controlled atmosphere, the sensor demonstrates high sensitivity and selectivity, by discriminating NO2 and NH3 without being interfered with CO and C3H8. A very high response (30%) is obtained at 50 ppb of NO2. Compare to the state of the art, 25% reached for 200 ppb, this significant response indicates that the lowest detectable NO2 concentration by our device is greatly below 20 ppb. In addition, the recovery of the sensor is achieved naturally at room temperature, without flushing or specific illumination for the NO2 molecules desorption, with reliability over 6 months. The SiNW are developed through a top down approach: combination of photolithography to control the number, spacing and position of each nanowire and so achieve a high reproducibility and sacrificial oxidation to master the diameter. The device is composed by two symmetrical aluminium contacts (low access resistance) at each extremity of the NWs, including a top contact done by air bridge approach. In addition, this CMOS approach is top-down and bottom-up compatible, leaving a choice for the selection of appropriate materials in function of the target species

Vertical Junction-less Gate-All-Around Transistors with Reliable 3D Multilevel Contact Engineering for High Performance and Low Power Applications

A sub-20 nm Gate-all-around (GAA) p-type silicon nanowire array-based metal oxide semiconductor field-effect transistor (MOSFET) is presented in this paper. The transistors exhibit good Ion/Ioff characteristics and allow for the full control of the short-channel effects as revealed by their low drain-induced barrier lowering (≈10 mV/V) and near-ideal subthreshold swing (≈74 mV/dec). We show that the wider the nanowire, the higher the drive current will be while on the other hand the Ion/Ioff degrades. We study the impact of the temperature variations on the static characterization of doped Junctionless GAA P-MOSFET and compare it to Schottky barrier P-MOSFET. The JunctionLessTransistor (JLT) shows a similar trend as the Schottky barrier MOSFET for their figure of merits as observed by the subthreshold slope, DIBL and threshold voltage for decreasing temperature down to 100 K

Overcoming Limits in Nano-Optical Simulations, Design and Experiments Using Deep Learning

International audienceSubwavelength small particles can be tailored to fulfill manifold functionalities when interacting with light. During the past twenty years, tremendous research efforts have therefore been put into the field of nano-optics, leading to astonishing results and applications like flat optics, optical cloaking or negative index meta-materials. However, there are physical and/or methodological constraints which have proven hard to overcome. For instance, the optical diffraction limit is a difficult obstacle in many applications ranging from microscopy to optical information storage. In nanooptics modeling, inverse problems like the rational design of nano-structures are another example for a difficult tasks. We show how problems that were until recently considered very hard to solve, can be tackled efficiently using methods of artificial intelligence (AI) and specifically deep learning

Overcoming Limits in Nano-Optical Simulations, Design and Experiments Using Deep Learning

International audienceSubwavelength small particles can be tailored to fulfill manifold functionalities when interacting with light. During the past twenty years, tremendous research efforts have therefore been put into the field of nano-optics, leading to astonishing results and applications like flat optics, optical cloaking or negative index meta-materials. However, there are physical and/or methodological constraints which have proven hard to overcome. For instance, the optical diffraction limit is a difficult obstacle in many applications ranging from microscopy to optical information storage. In nanooptics modeling, inverse problems like the rational design of nano-structures are another example for a difficult tasks. We show how problems that were until recently considered very hard to solve, can be tackled efficiently using methods of artificial intelligence (AI) and specifically deep learning