Damage analysis of pressure pipes under high temperature and variable pressure conditions

The problem of non-linear stress analysis of creeping reinforced pipes under constant pressure has been treated in a recent work [1]. In the present work, a damage accumulation analysis of the above problem is attempted taking into account the non-linear distribution of the stresses as well as non-linear damage accumulation under variable pressure and/or temperature conditions. For the stress analysis a non-linear differential equation is used to derive the stress concentration in critical locations of power pipes reinforced by rigid rings which are distributed along their axis. Due to step-wised temperature and internal pressure of the pipe, the damage accumulation is predicted by using a damage function specified with respect to damage parameter derived by the stress versus Larson-Miller coefficient curve. Advantages of the proposed methodology are: (a) the 2-D creep stress analysis incorporates mechanical behaviours of material derived by uniaxial tests, (b) the predicted damage accumulation due to the variable pressure takes into account the previous damage history as well as the loading order effect

Quantitative Characterization of the Software Layer of a HW/SW Co-Designed Processor

HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design.Peer ReviewedPostprint (author's final draft

HW/SW Co-designed Processors: Challenges, Design Choices and a Simulation Infrastructure for Evaluation

Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. However, HW/SW co-designed processors need to address some key challenges such as startup delay, providing high performance with simple hardware, translation/optimization overhead, etc. before they can become mainstream. A fundamental requirement for evaluating different design choices and trade-offs to meet these challenges is to have a simulation infrastructure. Unfortunately, there is no such infrastructure available today. Building the aforementioned infrastructure itself poses significant challenges as it encompasses the complexities of not only an architectural framework but also of a compilation one. This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. Furthermore, the paper presents DARCO, a simulation infrastructure to enable research in this domain.Peer ReviewedPostprint (author's final draft

The effects of upper body blood flow restriction training on muscles located proximal to the applied occlusive pressure: A systematic review with meta-analysis

Background Blood flow restriction combined with low load resistance training (LL-BFRT) is associated with increases in upper limb muscle strength and size. The effect of LL-BFRT on upper limb muscles located proximal to the BFR cuff application is unclear. Objective The aim of this systematic review was to evaluate the effect of LL-BFRT compared to low load, or high load resistance training (LL-RT, HL-RT) on musculature located proximal to cuff placement. Methods Six electronic databases were searched for randomized controlled trials (RCTs). Two reviewers independently evaluated the risk of bias using the PEDro scale. We performed a meta-analysis using a random effects model, or calculated mean differences (fixed-effect) where appropriate. We judged the certainty of evidence using the GRADE approach. Results The systematic literature searched yielded 346 articles, of which 9 studies were eligible. The evidence for all outcomes was of very low to low certainty. Across all comparisons, a significant increase in bench press and shoulder flexion strength was found in favor of LL-BFRT compared to LL-RT, and in shoulder lean mass and pectoralis major thickness in favor of the LL-BFRT compared to LL-RT and HL-RT, respectively. No significant differences were found between LL-BFRT and HL-RT in muscle strength. Conclusion With low certainty LL-BFRT appears to be equally effective to HL-RT for improving muscle strength in upper body muscles located proximal to the BFR stimulus in healthy adults. Furthermore, LL-BFRT may induce muscle size increase, but these adaptations are not superior to LL-RT or HL-RT

The effects of upper body blood flow restriction training on muscles located proximal to the applied occlusive pressure: A systematic review with meta-analysis.

BackgroundBlood flow restriction combined with low load resistance training (LL-BFRT) is associated with increases in upper limb muscle strength and size. The effect of LL-BFRT on upper limb muscles located proximal to the BFR cuff application is unclear.ObjectiveThe aim of this systematic review was to evaluate the effect of LL-BFRT compared to low load, or high load resistance training (LL-RT, HL-RT) on musculature located proximal to cuff placement.MethodsSix electronic databases were searched for randomized controlled trials (RCTs). Two reviewers independently evaluated the risk of bias using the PEDro scale. We performed a meta-analysis using a random effects model, or calculated mean differences (fixed-effect) where appropriate. We judged the certainty of evidence using the GRADE approach.ResultsThe systematic literature searched yielded 346 articles, of which 9 studies were eligible. The evidence for all outcomes was of very low to low certainty. Across all comparisons, a significant increase in bench press and shoulder flexion strength was found in favor of LL-BFRT compared to LL-RT, and in shoulder lean mass and pectoralis major thickness in favor of the LL-BFRT compared to LL-RT and HL-RT, respectively. No significant differences were found between LL-BFRT and HL-RT in muscle strength.ConclusionWith low certainty LL-BFRT appears to be equally effective to HL-RT for improving muscle strength in upper body muscles located proximal to the BFR stimulus in healthy adults. Furthermore, LL-BFRT may induce muscle size increase, but these adaptations are not superior to LL-RT or HL-RT

HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation

Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. However, HW/SW co-designed processors need to address some key challenges such as startup delay, providing high performance with simple hardware, translation/optimization overhead, etc. before they can become mainstream. A fundamental requirement for evaluating different design choices and trade-offs to meet these challenges is to have a simulation infrastructure. Unfortunately, there is no such infrastructure available today. Building the aforementioned infrastructure itself poses significant challenges as it encompasses the complexities of not only an architectural framework but also of a compilation one. This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. Furthermore, the paper presents DARCO, a simulation infrastructure to enable research in this domain.Peer Reviewe

Quantitative characterization of the software layer of a HW/SW co-designed processor

HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design.Peer Reviewe

Modelling HW/SW Co-Designed Processors

This paper presents DARCO, an extensible platform for modelling HW/SW co-designed processors with different guest and host ISAs. Its Emulation Software Layer (ESL) provides staged compilation, which translates and optimizes x86 binaries to run on a PowerPC processor. In addition to the functional models, DARCO provides timing simulators and a powerful debugging toolchain. DARCO has a functional emulation speed of 8 million x86 instructions per second

Abstracts of the 9th International Organisation of Physical Therapy in Mental Health Conference

This book contains the abstracts of the papers presented at the 9th International Organisation of Physical Therapy in Mental Health Conference, Organized by the International Organisation of Physical Therapy in Mental Health and Greek Scientific Section “Physiotherapy in Mental Health” of PanHellenic Physiotherapists’ Association, held on 4–6 May 2022. It is the biannual conference of the International Organization of Physical Therapy in Mental Health (IOPTMH), and we answered with success the question: Physiotherapy in mental health; what’s next? The highly qualified scientific program, the reputable presenters, and the venue altogether form a powerful motivation for both physiotherapists and other mental health professionals to attend this conference. Conference Title: 9th International Organisation of Physical Therapy in Mental Health ConferenceConference Theme: Physiotherapy in mental health; what’s next?Conference Date: 4–6 May 2022Conference Location: Crowne Plaza Athens - City Centre Hotel, 50, Michalakopoulou Str. GR 11528 AthensConference Organizer: International Organisation of Physical Therapy in Mental Health and Greek Scientific Section “Physiotherapy in Mental Health” of PanHellenic Physiotherapists’ AssociationConference Secretariat - Public Relations: Alpha Public Relations and Integrated Marketing S.A., 55, Pytheou Str. GR 11743 Athen