Picosecond Avalanche Detector — working principle and gain measurement with a proof-of-concept prototype

The Picosecond Avalanche Detector is a multi-junction silicon pixel detector based on a (NP)drift(NP)gain structure, devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamp capability. It uses a continuous junction deep inside the sensor volume to amplify the primary charge produced by ionizing radiation in a thin absorption layer. The signal is then induced by the secondary charges moving inside a thicker drift region. A proof-of-concept monolithic prototype, consisting of a matrix of hexagonal pixels with 100 μm pitch, has been produced using the 130 nm SiGe BiCMOS process by IHP microelectronics. Measurements on probe station and with a 55Fe X-ray source show that the prototype is functional and displays avalanche gain up to a maximum electron gain of 23. A study of the avalanche characteristics, corroborated by TCAD simulations, indicates that space-charge effects due to the large primary charge produced by the conversion of X-rays from the ^55Fe source limits the effective gain

Testbeam results of the Picosecond Avalanche Detector proof-of-concept prototype

The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 μm pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm2, respectively. In this first prototype the time resolution depends significantly on the distance from the center of the pixel, varying at the highest power consumption measured between 13 ps at the center of the pixel and 25 ps in the inter-pixel region

Testbeam Results of the Picosecond Avalanche Detector Proof-Of-Concept Prototype

The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 {\mu}m pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm^2, respectively. In this first prototype the time resolution depends significantly on the distance from the center of the pixel, varying at the highest power consumption measured between 13 ps at the center of the pixel and 25 ps in the inter-pixel region

20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer of 350 {\Omega}cm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.Comment: 11 pages, 11 figure

Radiation Tolerance of SiGe BiCMOS Monolithic Silicon Pixel Detectors without Internal Gain Layer

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer with a resistivity of 350 {\Omega}cm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 x 10^14 n_eq /cm^2 . The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35 {^\circ}C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm^2, the time jitter of the most-probable signal amplitude was estimated to be 21 ps for proton fluence up to 6 x 10 n_eq/cm^2 and 57 ps at 1 x 10^16 n_eq/cm^2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 x 10^16 n_eq/cm^2.Comment: Submitted to JINS

Efficiency and time resolution of monolithic silicon pixel detectors in SiGe BiCMOS technology

A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 μm. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of (99.9$_{-0.2}$ $^{+0.1}$)% was measured together with a time resolution of (36.4 ± 0.8) ps at the highest preamplifier bias current working point of 150 μA and at a sensor bias voltage of 160 V. The ASIC was also characterized at lower bias voltage and preamplifier current.A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 $\mu$m. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of $\left(99.9^{+0.1}_{-0.2}\right)$% was measured together with a time resolution of $(36.4 \pm 0.8)$ps at the highest preamplifier bias current working point of 150 $\mu$A and at a sensor bias voltage of 160 V. The ASIC was also characterized at lower bias voltage and preamplifier current

Gain measurements of the first proof-of-concept PicoAD prototype with a 55Fe X-ray radioactive source

The Picosecond Avalanche Detector is a multi-junction silicon pixel detector devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamping capability. A proof-of-concept prototype of the PicoAD sensor has been produced by IHP microelectronics. Measurements with a 55Fe X-ray radioactive source show that the prototype is functional with an avalanche gain up to a maximum electron gain of 23

Radiation tolerance of SiGe BiCMOS monolithic silicon pixel detectors without internal gain layer

A monolithic silicon pixel prototype produced for theMONOLITH ERC Advanced project was irradiated with 70 MeV protons upto a fluence of 1 × 10$^{16}$1 MeV n$_{eq}$/cm$^{2}$. The ASIC contains a matrix ofhexagonal pixels with 100 μm pitch, readout by low-noise andvery fast SiGe HBT frontend electronics. Wafers with 50 μmthick epilayer with a resistivity of 350 Ωcm were used toproduce a fully depleted sensor. Laboratory tests conducted with a$^{90}$Sr source show that the detector works satisfactorily afterirradiation. The signal-to-noise ratio is not seen to change up tofluence of 6 × 10$^{14}$n$_{eq}$/cm$^{2}$. The signaltime jitter was estimated as the ratio between the voltage noise andthe signal slope at threshold. At -35°C, sensor bias voltageof 200 V and frontend power consumption of 0.9 W/cm$^{2}$, the timejitter of the most-probable signal amplitude was estimated to be σ$_{t}$$^{90}$Sr = 21 ps for proton fluence up to6 × 10$^{14}$n$_{eq}$/cm$^{2}$ and 57 ps at1 × 10$^{16}$n$_{eq}$/cm$^{2}$. Increasing the sensorbias to 250 V and the analog voltage of the preamplifier from 1.8to 2.0 V provides a time jitter of 40 ps at1 × 10$^{16}$n$_{eq}$/cm$^{2}$.A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 x 10^14 n_eq /cm^2 . The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35 {^∘}C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm^2, the time jitter of the most-probable signal amplitude was estimated to be 21 ps for proton fluence up to 6 x 10 n_eq/cm^2 and 57 ps at 1 x 10^16 n_eq/cm^2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 x 10^16 n_eq/cm^2

The CompactLight Design Study

CompactLight is a Design Study funded by the European Union under the Horizon 2020 research and innovation funding programme, with Grant Agreement No. 777431. CompactLight was conducted by an International Collaboration of 23 international laboratories and academic institutions, three private companies, and five third parties. The project, which started in January 2018 with a duration of 48 months, aimed to design an innovative, compact, and cost-effective hard X-ray FEL facility complemented by a soft X-ray source to pave the road for future compact accelerator-based facilities. The result is an accelerator that can be operated at up to 1 kHz pulse repetition rate, beyond today’s state of the art, using the latest concepts for high brightness electron photoinjectors, very high gradient accelerating structures in X-band, and novel short-period undulators. In this report, we summarize the main deliverable of the project: the CompactLight Conceptual Design Report, which overviews the current status of the design and addresses the main technological challenges