A CMOS implementation of a spike event coding scheme for analog arrays

This paper presents a CMOS circuit implementation of a spike event coding/decoding scheme for transmission of analog signals in a programmable analog array. This scheme uses spikes for a time representation of analog signals. No spikes are transmitted using this scheme when signals are constant, leading to low power dissipation and traffic reduction in a shared channel. A proof-of-concept chip was designed in a 0.35 mum process and experimental results are presented

Bio-inspired event coded configurable analog circuit block

An event coded configurable analog circuit block that forms the building block of a programmable analog array is presented. The de- sign of the event block is inspired from the behavior of biological neurons that process signals in analog domain and transmit them as spike events. In the configurable event block implemented here, no events are trans- mitted when the signals are relatively constant thereby leading to lower energy dissipation and better utilization of resources in analog arrays. The block diagram and the circuit schematics of the event coded configurable analog block are described. Application examples are presented to demonstrate the reconfigurability and functionality of the event coded circuit block

A programmable time event coded circuit block for reconfigurable neuromorphic computing

A generic programmable time event coded circuit which forms the building block for a reconfigurable neuromorphic array is implemented in analog VLSI.An array of programmable time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems 0.35 μm CMOS technology to demonstrate the functionality of the circuits in silicon

Computation in communication: spike event coding for programmable analog arrays

This paper presents the computation properties of an asynchronous spike event coding scheme employed for communicating signals between analog blocks in a programmable array. The computation is intrinsic to the spike event communication scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. Test results from a chip implemented using 0.35 μm CMOS technology are presented

Programmable analog VLSI architecture based upon event coding

A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array. The internal circuit schematics of the event block is presented. The event blocks in the array are programmed to perform as functional circuit blocks for neuromorphic and classical computations. A programmable array chip with 10 event blocks is fabricated using Austria Microsystems 0.35 mum CMOS technology to demonstrate the functionality of the circuits in silicon

An asynchronous spike event coding scheme for programmable analog arrays

This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-μm CMOS technology are presented

A programmable spike-timing based circuit block for reconfigurable neuromorphic computing

A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems 0.35um CMOS technology to demonstrate the functionality of the circuits in silicon