609 research outputs found
Synthesis and characterization of silver nanoarticles from extract of Eucalyptus citriodora
The primary motivation for the study to develop simple eco-friendly green synthesis of silver nanoparticles using leaf extract of Eucalyptus citriodora as reducing and capping agent. The green synthesis process was quite fast and silver nanoparticles were formed within 0.5 h. The synthesis of the particles was observed by UV-visible spectroscopy by noting increase in absorbance. Characterization of the particles was carried out by X-ray diffraction, FTIR and electron microscopy. The developed nanoparticles demonstrated that E. citriodora is good source of reducing agents. UV-visible absorption spectra of the reaction medium containing silver nanoparticles showed maximum absorbance at 460 nm. FTIR analysis confirmed reduction of Ag+ to Ag0 atom in silver nanoparticles. The XRD pattern revealed the crystalline structure of silver nanoparticles. The SEM analysis showed the size and shape of the nanoparticles. The method being green, fast, easy and cost effective can be recommended for large scale production of AgNPs for their use in food, medicine and materials
Aging Benefits in Nanometer CMOS Designs
This document is the Accepted Manuscript version of the following article: Daniele Rossi, Vasileios Tenentes, Sheng Yang, Saqib Khursheed, and Bashir M. Al-Hashimi, ‘Aging Benefits in Nanometer CMOS Designs’, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64 (3), May 2016. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.n this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.Peer reviewedFinal Accepted Versio
The impact of nutritional counselling on serum lipids, dietary and physical activity patterns of school children
Eighty-eight school children and their parents who had been counselled regarding appropriate dietary and activity patterns aimed at reducing serum cholesterol were followed-up 21 months later to determine changes in dietary and activity patterns and in serum lipid levels. The decline in serum total cholesterol ranged from 8 to 14% in the different age and sex groups (P \u3c 0.05 to P \u3c 0.001). Serum triglycerides did not change significantly. Cholesterol intake decreased 36% and 54% in 10-14 year old boys and girls respectively (P \u3e 0.001). The activity level increased significantly in both the 5-9 year and 10-14 year olds (P \u3c 0.05 to P \u3c 0.005). These results show that nutrition education can bring about a change in dietary and activity patterns, resulting in a decline in serum cholesterol levels
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs
Manufacturing defects that do not affect the functional
operation of low power Integrated Circuits (ICs) can
nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process
variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R ≳ 10MΩ(weak bridges) and bridges of R ≲ 10MΩ
(strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively
DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test
This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles
Reliable Power Gating with NBTI Aging Benefits
In this paper, we show that Negative Bias Temperature
Instability (NBTI) aging of sleep transistors (STs),
together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for power gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test-chip manufactured with a TSMC 65nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower Vth compared to the standard power switching fabric. This can be achieved by either re-designing the STs with the identified Vth value, or applying a proper forward body bias to the available power switching fabrics. Through HSPICE simulations, we show lifetime extension up to 21.4X and average static power reduction up to 16.3% compared to standard ST design approach, without additional area overhead. Finally, we show lifetime extension and several performance-cost trade-offs when a target maximum lifetime is considered
Diagnosis of power switches with power-distribution-network consideration
This paper examines diagnosis of power switches when the power-distribution-network (PDN) is considered as a high resolution distributed electrical model. The analysis shows that for a diagnosis method to perform high diagnosis accuracy and resolution, the distributed nature of PDN should not be simplified by a lumped model. For this reason, a PDN-aware diagnosis method for power switches fault grading is proposed. The proposed method utilizes a novel signature generation design-for-testability (DFT) unit, the signatures of which are processed by a novel diagnosis algorithm that grades the magnitude of faults. Through simulations of physical layout SPICE models, we explore the trade-offs of the proposed method between diagnosis accuracy and diagnosis resolution against area overhead and we show that 100% diagnosis accuracy and up to 98% diagnosis resolution can be achieved with negligible cost
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating
In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%
- …