The Impact of Submicron 10x Reticle Defects on Images Printed with a 0.28 NA G-Line Stepper

A lOX reticle was produced with programmed defects of both polarities varying size, proximity to adjacent features, and feature sizes. The defects were imaged in various resist materials over silicon, silicon dioxide, silicon nitride, polysilicon, aluminum, and a 1X chrome mask using a GCA/Mann 4800 stepper. Results obtained using optical and scanning electron microscopy demonstrated that reticle defects as small as 1.0 micron, when in proximity to a feature, will cause linewidth variation in the printed image. The resist film and underlying substrate did affect the linewidth variation. Defocus and over/under exposure also influenced the severity of damage created by reticle defects. A two—dimensional aerial image simulator SPLAT, which is a version of SAMPLE, was used to simulate the optical interactions of defects with adjacent features

Process development of an analog/digital mixed-mode BiCMOS system at RIT

The development of an analog/digital mixed-mode BiCMOS process is presented. The process uses the RIT factory n-well CMOS process as its baseline process. The process is tailored to meet the requirements of an analog/digital system, while minimizing process complexity and maximizing compatibility with the established CMOS process. The process development includes determining the device requirements for the BiCMOS process, evaluating the established CMOS process, and integrating the additional process steps into the baseline process. TMA SUPREM III 1-D Process Analysis Program and RIT\u27s processing history are used as guidelines, keeping manufacturability an important issue. An integrated test chip is developed to measure the performance of the process and to compare measured results with modelling simulations. The test chip includes test structures for each masking level, along with test circuits that are designed using CMOS, bipolar, and BiCMOS technologies, which perform analog and digital functions. The process is implemented into the RIT factory, utilizing the WIPTRACK tracking system. Each processing step is entered into the system with complete instructions. Real-time measurement data is entered into the system at each step by operators under the supervision of the process engineer. Analysis of the test structures and test circuits will demonstrate the performance of the designed process

A TCAD calibrated approach for on-state modeling of amorphous oxide semiconductor TFTs

Amorphous oxide semiconductor materials such as IGZO exhibit electrical characteristics that are not well represented by conventional device models due to the presence of band-tail states (BTS). Common parameters such as threshold voltage and channel mobility that are extracted from measured electrical characteristics can be misrepresentative due to discrepancies between the device operation and the chosen operational model. Compact models that have been developed for model accuracy and circuit simulation efficiency offer limited insight on the underlying device physics involved. The focus of this work is a model for device engineering which maintains a close physical connection to device operation, and captures the 2D influence of both the gate and drain bias conditions on the ionization and deionization of acceptor-like BTS near the conduction band edge. A device model for the on-state operation of accumulation-mode IGZO TFTs was recently presented as an adaptation of a Level 2 SPICE (L2S) model [1]. The model introduced channel charge adjustments which account for the occupancy of BTS as influenced by the gate and drain voltage, and provided an exceptional match to both simulated and measured device characteristics. However the integrity of the model as assessed by the ability to discriminate between the influence of BTS and short-channel effects (SCE) was compromised as the device channel length was decreased. Accumulation-mode devices are susceptible to the onset of SCE at relatively long channel lengths due to the lack of a source-channel junction barrier. While the subthreshold region may show minimal influence of drain induced barrier lowering (DIBL), the on-state may exhibit an effective decrease in the triode region of operation. A new model is presented which incorporates this on-state DIBL along with channel length modulation, and demonstrates improved discrimination between BTS and SCE in the model fit at device channel lengths L ≥ 3 µm. Silvaco® Atlas™ TCAD played a key role in device model development. A long-channel reference device was used to establish the impact of SCE on short devices, which was then modeled by and terms in associated triode and saturation regions of operation. For channel lengths L \u3c 3 µm, a lumped SCE multiplier was used to represent short-channel behavior, followed by the application of BTS parameters for channel charge adjustments. Modeling results derived from both simulated and measured TFT characteristics will be presented. [1] K.D. Hirschman, T. Mudgal, E. Powell and R.G. Manley, ECS Trans. 86, 153 (2018

Microelectronic engineering education for emerging frontiers

With the support provided by the National Science Foundation and RIT Provost’s vision for providing flexible curricula, the department of Microelectronic Engineering has instituted new and enhanced program initiatives – (1) offering a semiconductor processing minor for other science and engineering programs promoting access to state-of-the art semiconductor fabrication facilities to students from other programs; (2) crafting a five course elective sequence within the existing curriculum by eliminating legacy material and course consolidation; (3) developing a concentration program in nanotechnology and MEMS; (4) outreach programs for targeting larger and diverse participation in preparing workforce for the nation’s future high tech industry; (5) enhance student learning through co-op and service. The mission is to generate multi faceted work force for the future semiconductor technologies and emerging frontiers spinning off from microelectronics, while simultaneously promoting enrollment particularly from women and minority students

Flash lamp annealed polycrystalline silicon as a potential candidate for large panel manufacturing

The flat-panel display industry is in pursuit of TFT manufacturing processes which are cost-effective, easily scalable to large glass panels, and meet the performance requirements of advanced display products. While excimer laser anneal (ELA) low-temperature polycrystalline silicon (LTPS) can offer exceptional TFT performance, a lower grade LTPS may still satisfy product requirements at a lower production cost. Flash-Lamp Annealing (FLA) is an emerging candidate for the manufacture of LTPS. Multi-lamp exposure systems with high repetition pulse rates would potentially offer significant advantages in manufacturing throughput and cost over ELA. Techniques to overcome challenges that have hindered device scaling and reduction in variation of device operation are under investigation. The following presents a status update on the development of FLA Polycrystalline Silicon (FLAPS) technology. The FLA equipment used for this work was a NovaCentrix PulseForge 3300 system, capable of uniform exposure of a 7 cm x 12 cm area at intensities as high as 50 kW/cm2 over microseconds pulse duration. PMOS TFTs were fabricated using combinations of FLA, ion implantation and furnace annealing to define the source/drain and channel regions. Predefined polygons of 60 nm thick amorphous silicon vertically sandwiched between layers of SiO2 were crystallized on Corning Lotus NXT display glass using single-pulse FLA exposure. The amorphous silicon melts while absorbing a sufficient fraction of the xenon emission spectrum, and becomes polycrystalline while staying within the thermal constraints of the underlying glass substrate. Boron dopant ions were implantation into the source/drain regions defined by lithographic patterning or a self-aligned gate strategy. Boron activation was realized by combinations of FLA, furnace annealing, and pre-amorphization using an electrically inactive species. FLA conditions following dopant introduction avoided silicon melting which causes significant lateral diffusion. Representative electrical characteristics are shown in figure 1. While the device operation demonstrates a general dependence on the degree of dopant activation, observations on the electrical characteristics indicate a complex relationship between defect states and the specific implant/activation strategy applied. The influence of doping strategy on both device performance and resistance to failure is the primary focus of this work. Additional experiments involving variations in the FLAPS morphology will also be discussed. Please click Additional Files below to see the full abstract

Donor activation in boron and phosphorus implanted self-aligned bottom-gate Igzo Tfts

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a‑Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode [1,2]. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance, however this usually requires several microns of gate-to-source/drain overlap to ensure such behavior. Please click Download on the upper right corner to see the full abstract

Simulation analysis of dispatching rules for automated material handling systems and processing tools in semiconductor fabs

Abstract – A critical aspect of semiconductor manufacturing is the design and analysis of material handling and production control polices to optimize fab performance. This research utilizes two simulations of SEMATECH fab data of actual production fabs. The hypothesis of this study is that both vehicle and machine dispatching rules and their interaction will have significant impact on fab performance. To test this hypothesis, a full factorial design experiment is performed. The vehicle and machine dispatching rules as well as their interaction are shown to have a significant impact

Instances and connectors : issues for a second generation process language

This work is supported by UK EPSRC grants GR/L34433 and GR/L32699Over the past decade a variety of process languages have been defined, used and evaluated. It is now possible to consider second generation languages based on this experience. Rather than develop a second generation wish list this position paper explores two issues: instances and connectors. Instances relate to the relationship between a process model as a description and the, possibly multiple, enacting instances which are created from it. Connectors refers to the issue of concurrency control and achieving a higher level of abstraction in how parts of a model interact. We believe that these issues are key to developing systems which can effectively support business processes, and that they have not received sufficient attention within the process modelling community. Through exploring these issues we also illustrate our approach to designing a second generation process language.Postprin

Designing for the Infrastructure of the Supply Chain of Malay Handwoven Songket in Terengganu

The growing HCI interest in developing contexts and cultural craft practices is ripe to focus on their under-explored homegrown sociotechnical infrastructures. This paper explores the creative infrastructural actions embedded within the practices of songket's supply chain in Terengganu, Malaysia. We report on contextual interviews with 92 participants including preparation workers, weavers, designers, merchants, and customers. Findings indicate that increased creative infrastructural actions are reflected in these actors' resourcefulness for mobilizing information, materials, and equipment, and for making creative artifacts through new technologies weaved within traditional practices. We propose two novel approaches to design in this craft-based infrastructure. First, we explore designing for the social layer of infrastructure and its mutually advantageous exploitative relationships rooted in culture and traditions. Second, we suggest designing for roaming value-creation artifacts, which blend physical and digital materializations of songket textile design. Developed through a collaborative and asynchronous process, we argue that these artifacts represent less-explored vehicles for value co-creation, and that sociotechnical infrastructures as emerging sites of innovation could benefit from HCI research

Naming and War in Modern Germany

This paper analyzes naming behavior in Germany in the context of rapid social change. It begins with an overview of general developments in naming in Germany over the last one hundred years, based on data from the German Socio-Economic Panel Study (SOEP), which supplies us with almost 45,000 datasets. The paper focuses on the periods of World War II and the Cold War since we conclude that general developments in naming were disrupted by these two phenomena. Wartime brings accelerated social change in its wake and people react to this social change - often on an apparently individual level. Here, our findings are in accordance with established sociological theories.Publisher's website: http://maneypublishing.com/index.php/journals/nam