A Sub-1-V, 350-uW, 6.5-dB Integrated NF Low-IF Receiver Front-End for IoT in 28-nm CMOS

This letter presents a highly efficient low-intermediate frequency receiver front-end for Internet-of-Things applications. The lownoise trans-impedance amplifier (LNTA) combines a transformer-based network for scaling up the source impedance together with passive gmboosting and current-reuse techniques to achieve better noise and 12× current saving compared with a common-gate (CG) stage. A complex channel-selection filter with center frequency and passband of 2 and 1.4 MHz, respectively, is implemented after the passive mixer with a gmboosted CG stage. Built in 28-nm CMOS, the proposed receiver occupies an active area of 0.1 mm 2 , it is supplied with 0.9 V and consumes only 350 μW, while showing a minimum NF of 6.2 dB at the channel of interest. The RF performance of the proposed receiver is very competitive with the state-of-the-art ultralow-power receivers, while it consumes the lowest power

An ultra low power OTA with improved unity gain bandwidth product

An operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) and hybrid compensation technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair. Two separate capacitors are employed for the OTA compensation where one of them is used in a signal path and the other one in a non-signal path. The circuit is designed in the 0.18μm CMOS TSMC technology. The proposed design technique shows remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair OTAs. The Hspice simulation results show that the amplifier has a 92dB open-loop DC gain and a unity gain-bandwidth of 135kHz while operating at 0.4V supply voltage. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical and bio-implantable applications

High Performance Building Blocks for SAW-Less Transceivers & Design of Ultra-Low Power Receiver for Wireless Sensor Networks

To keep up with the increasing demand for higher data rates, 5G will introduce new multiple-input multiple-output (MIMO) techniques and enhance existing ones such as beamforming and diversity. This, combined with larger bandwidths, more complex modulations and increased number of bands and modes will greatly increase terminal complexity. Presently, to meet the stringent specifications of frequency division duplexing (FDD) cellular standards, for each operating band, a highly selective duplexer (based on surface acoustic wave (SAW) filters) is used to connect receiver and transmitter to the shared antenna. In recent years, various interference mitigation techniques have been introduced with the goal of replacing the off-chip filters with tunable on-chip counterparts, thus significantly reducing system cost and complexity. Nonetheless, given the extremely challenging interference scenario, this is still an open issue. In the first part of this thesis, a highly linear low noise transconductance (LNTA) is proposed to be easily integrated in an advanced wireless receiver with a self-interference cancellation performance that significantly improves state-of-the-art while removing bulky component like SAW filter. The proposed LNTA demonstrated an antenna input referred IIP3 of 27 dBm while consuming only 14 mW and facilitating removing bulky and off-chip components like SAW filter leading to considerably cost benefit. The increasing demand for wearable wireless devices has motivated the research on ultra-low power (ULP) transceivers. Some ULP applications, such as wireless medical telemetry and Wearable-Wireless Sensor Networks (W-WSN) require the portable devices to operate from a single Lithium Ion battery or to use energy harvested from the environment. This makes low supply voltage operation an additional stringent requirement. For WSN, it is especially critical to have a ULP receiver since the sensor is mostly operating in the receive mode rather than in transmit mode. As a consequence, its overall power consumption is determined by the receiver chain. Low Noise Amplifier (LNA) is the first block of the receiver chain and generally considered as one of the most power hungry blocks due to performing simultaneous tasks. In Bluetooth Low Energy (BLE) application, the RF spec is very relax in the favor of reducing dissipation power. Thanks to introducing a novel and efficient current reuse technique and also passive gm boosting, the LNA input impedance is reduced by factor of 24 compared to a single transistor using the same current. Hence, the proposed LNA with RF spec which far exceeded the requirements of intended application while consuming only 30 μW is presented in the second part of this thesis. In fact, the, overall performance of the proposed LNA is almost three times better than the stat of the art. Furthermore, thanks to extensively utilizing current reuse scheme and employing forward back gate biasing in advanced technology of 22 nm FD-SOI, it enables to design an ULP receiver for BTLE application. The proposed receiver consumes much less power compared to state-of-the-art receivers and far exceed the requirements of wireless sensor network standards such as BT-LE. It can operate with supply voltage as low as 0.4V while consumes only 100 μW with much smaller chip area, better NF and better linearity compares to the-state-of-the-art.To keep up with the increasing demand for higher data rates, 5G will introduce new multiple-input multiple-output (MIMO) techniques and enhance existing ones such as beamforming and diversity. This, combined with larger bandwidths, more complex modulations and increased number of bands and modes will greatly increase terminal complexity. Presently, to meet the stringent specifications of frequency division duplexing (FDD) cellular standards, for each operating band, a highly selective duplexer (based on surface acoustic wave (SAW) filters) is used to connect receiver and transmitter to the shared antenna. In recent years, various interference mitigation techniques have been introduced with the goal of replacing the off-chip filters with tunable on-chip counterparts, thus significantly reducing system cost and complexity. Nonetheless, given the extremely challenging interference scenario, this is still an open issue. In the first part of this thesis, a highly linear low noise transconductance (LNTA) is proposed to be easily integrated in an advanced wireless receiver with a self-interference cancellation performance that significantly improves state-of-the-art while removing bulky component like SAW filter. The proposed LNTA demonstrated an antenna input referred IIP3 of 27 dBm while consuming only 14 mW and facilitating removing bulky and off-chip components like SAW filter leading to considerably cost benefit. The increasing demand for wearable wireless devices has motivated the research on ultra-low power (ULP) transceivers. Some ULP applications, such as wireless medical telemetry and Wearable-Wireless Sensor Networks (W-WSN) require the portable devices to operate from a single Lithium Ion battery or to use energy harvested from the environment. This makes low supply voltage operation an additional stringent requirement. For WSN, it is especially critical to have a ULP receiver since the sensor is mostly operating in the receive mode rather than in transmit mode. As a consequence, its overall power consumption is determined by the receiver chain. Low Noise Amplifier (LNA) is the first block of the receiver chain and generally considered as one of the most power hungry blocks due to performing simultaneous tasks. In Bluetooth Low Energy (BLE) application, the RF spec is very relax in the favor of reducing dissipation power. Thanks to introducing a novel and efficient current reuse technique and also passive gm boosting, the LNA input impedance is reduced by factor of 24 compared to a single transistor using the same current. Hence, the proposed LNA with RF spec which far exceeded the requirements of intended application while consuming only 30 μW is presented in the second part of this thesis. In fact, the, overall performance of the proposed LNA is almost three times better than the stat of the art. Furthermore, thanks to extensively utilizing current reuse scheme and employing forward back gate biasing in advanced technology of 22 nm FD-SOI, it enables to design an ULP receiver for BTLE application. The proposed receiver consumes much less power compared to state-of-the-art receivers and far exceed the requirements of wireless sensor network standards such as BT-LE. It can operate with supply voltage as low as 0.4V while consumes only 100 μW with much smaller chip area, better NF and better linearity compares to the-state-of-the-art

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phase-tracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm2 and consumes only $350~{\mu }\text{W}$ from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power

Design and Analysis of 2.4 GHz 30 μW CMOS LNAs for Wearable WSN Applications

To meet the requirements of wearable wireless sensor networks, the power dissipation of the RF transceiver has to be drastically reduced. This paper presents two ultra-low power low noise amplifiers (LNAs) with RF performance exceeding the requirement of the intended application. In the first LNA, by reusing the current several times and employing passive gm boosting, the LNA input impedance is reduced by a factor of 24 compared with a single transistor using the same current. The feasibility of passive gm boosting for designing an ultra-low supply voltage LNA is also investigated. Limitations of both LNAs, including NF, non-linearity, and stability in a 40-nm CMOS technology are also investigated. The proposed LNAs consume only 30 μW of power, operate with 0.8 V and 0.18 V and show NF of 3.3 and 5.2 dB, respectively. Using a widely accepted figure-of-merit for LNAs, the proposed circuit is almost three times better than the best previously reported sub-mW LNA

Design Considerations for a Sub-mW Wireless Medical Body-Area Network Receiver Front End

Wireless medical body-area networks are used to connect sensor nodes that monitor vital parameters. The radio consumes a large portion of the sensor energy budget, and hence its power dissipation should be minimized. The low-noise amplifier (LNA) is an important component of the receiver, and must guarantee low-noise amplification and impedance matching. In this work, an ultra-low-voltage ultra-low-power LNA is proposed that, thanks to the proposed transformer-based gate boosting technique, has a reduced current consumption of only 160 μA and can operate with a supply as low as 0.18 V. The LNA was designed using 40 nm Complementary Metal-Oxide Semiconductor (CMOS) technology and features a voltage gain of 14 dB, 5.2 dB NF and −8.6 dBm IIP3. This performance is comparable to a prior work by the same authors, but with the minimum supply voltage reduced by a factor of 4x