A low-power/low-noise readout circuit for integrated capacitive sensors

A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-mu W average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8% linearity error and 0.01 fF/degrees C temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing

A low-power CMOS VLSI circuit for signal conditioning in integrated capacitive sensors

Capacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire bonding in employed instead, to interconnect sensor and IC dies. In such cases, sensor capacitance is comparable or even smaller than the parasitic interconnection capacitance, while interconnection parasitic resistance inserts additional signal distortion. The signal-conditioning IC must be designed to compensate for these parasitic effects. Switched-Capacitor IC's may fulfil such specifications but the use of several operational amplifiers and intricate clocking schemes increase design complexity, die-size, and power consumption, which is inappropriate for wireless applications. In this work a low-power Switched-Capacitor IC for sub-fF capacitance measurements is presented. The proposed design requires two non-overlapping clocks but no operational amplifiers. It shows excellent robustness against interconnection parasitics, transistor dimensional mismatches, temperature, and process variations. © 2004 IEEE

A new SOI monolithic capacitive sensor for absolute and differential pressure measurements

In the present work, a new monolithic capacitive pressure sensor is being introduced. The sensor is manufactured according to a custom, 15-step SOI process. The process primarily offers great flexibility as far as sensor design is concerned. Absolute or differential pressure sensing is possible by simply arranging proper sensor package. Measurement sensitivity and span are easily regulated over a wide range of values by setting one-single design parameter. Attention is paid to avoid p-n junction formation in order to improve the sensor robustness against temperature increase and allow high-temperature post-processing without doping profile degradation. The presented design allows the implementation of an ordinary p-well CMOS post-process. Sensitivity of 2 mV/kPa, within a span of 180 kPa (2%) and a bandwidth of 25 kHz, is achievable by means of a CMOS switched-capacitor ASIC that is developed and presented here. Significant care has been taken for the ASIC performance to depend as less as possible on CMOS process and transistor-parameter variations that increase due to poor uniformity of the transistor substrate. Moreover, a state-of-the-art design is implemented for the circuit to provide robustness against parasitic capacitances connected in parallel with sensing capacitors. Implementation of additional analog signal processing improves the aforementioned accuracy at a significant extend. The sensors main applications include medical devices such as sphygmomanometers and respirators that require high reliability and biocompatibility. (C) 2005 Elsevier B.V. All rights reserved

Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuit's major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit. ©2004 IEEE

A statistically-based engine for P/G network optimization

The problem of optimum design of general (tree or graph-based) power distribution networks with respect to the voltage drop effect is addressed in this paper. A rigorous formulation based on linear circuit theory is established for the relevant constrained optimization problem, so that the resultant network occupies the minimum possible area under specific voltage drop constraints at all IC functional blocks. The necessary maximum current estimates for the optimization procedure are accurately obtained - by statistical means - from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit

A design flow for the precise identification of the worst-case voltage drop in power grid analyses

Modern IC designs contain hundreds of millions of transistors and new implementations of multi core chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow based on innovative results from recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine within an industrial EDA flow for performing power grid verification using a custom hierarchical design. © 2008 IEEE

An RTL-to-grid design flow for power grid verification based on a statistical estimation engine

The most important reliability problem of modern power distribution networks is the voltage drop or IR-drop problem. In this paper we present a design flow based on industrial tools for power grid verification, where the grid is modeled as a linear resistive network and the necessary maximum current estimates are statistically obtained by recent advances in the field of extreme value theory. Experimental results include the verification of power grid for a choice of different real designs. © 2006 IEEE

Antibody afucosylation augments CD16-mediated serial killing and IFN gamma secretion by human natural killer cells

One mechanism by which monoclonal antibodies (mAb) help treat cancer or autoimmune disease is through triggering antibody-dependent cellular cytotoxicity (ADCC) via CD16 on Natural Killer (NK) cells. Afucosylation is known to increase the affinity of mAbs for CD16 on NK cells and here, we set out to assess how mAb afucosylation affects the dynamics of NK cell interactions, receptor expression and effector functions. An IgG1 version of a clinically important anti-CD20 mAb was compared to its afucosylated counterpart (anti-CD20-AF). Opsonization of CD20-expressing target cells, 721.221 or Daudi, with anti-CD20-AF increased NK cell cytotoxicity and IFNγ secretion, compared to anti-CD20. The afucosylated mAb also caused a more rapid and greater loss of CD16 from NK cell surfaces. Loss of CD16 has recently been shown to be important for NK cell detachment and sequential engagement of multiple target cells. Here, live-cell time-lapse microscopy of individual cell-cell interactions in an aqueous environment and a three-dimensional matrix, revealed that anti-CD20-AF induced more rapid killing of opsonized target cells. In addition, NK cells detached more quickly from target cells opsonized with anti-CD20-AF compared to anti-CD20, which increased engagement of multiple targets and enabled a greater proportion of NK cells to perform serial killing. Inhibition of CD16 shedding with TAPI-0 led to reduced detachment and serial killing. Thus, disassembly of the immune synapse caused by loss of cell surface CD16 is a factor determining the efficiency of ADCC and antibody afucosylation alters the dynamics of intercellular interactions to boost serial killing

Characterization tools for mechanical probing of biomimetic materials

The possibility to fully heal damaged or failing tissues and organs is one of the major challenges of modern medicine. Several approaches have been proposed, either using tissue engineered functional substitutes or inducing the body to self-repair, exploiting its innate regenerative potential. In any case, a crucial step for the success of therapy is provided by the design of a suitable scaffold, capable to sustain cellular growth and induce the differentiation towards the lineage of interest. A growing body of evidence suggests that the most affordable way to design an effective scaffold is to exploit a biomimetic approach, trying to emulate the characteristics of the natural environment. Moreover, it has been pointed out that not only the chemical nature of the material is relevant to this process but also its physical and, in particular, mechanical properties. Mapping the elasticity of a living tissue is becoming more and more relevant in the rational design of next generation biomimetic scaffolds, and the exploitation of advanced tools is required to achieve sub-μm resolution, comparable to the length scale probed by a single living cell