A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems

In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use efficiently the full potential of MLC STTRAM. We exploit the asymmetric nature of the MLC storage scheme to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other is write-friendly. Furthermore, we propose to opportunistically deactivate ways in underutilized sets to convert MLC to Single-Level Cell (SLC) mode, which features overall better performance and lifetime. Our ultimate goal is to build a cache architecture that combines the capacity advantages of MLC and performance/energy advantages of SLC. Our experiments show an improvement of 43% in total numbers of conflict misses, 27% in memory access latency, 12% in system performance, and 26% in LLC access energy, with a slight degradation in cache lifetime (about 7%) compared to an SLC cache

Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy

[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scaling. Cache memories consume a sizable part of this power, particularly due to leakage energy. STT-RAM is one of several new memory technologies that have been proposed in order to improve power while preserving performance. It features high density and low leakage, but at the expense of write energy and performance. This article explores the use of STT-RAM--based scratchpad memories that trade nonvolatility in exchange for faster and less energetically expensive accesses, making them feasible for on-chip implementation in embedded systems. A novel multiretention scratchpad partitioning is proposed, featuring multiple storage spaces with different retention, energy, and performance characteristics. A customized compiler-based allocation algorithm suitable for use with such a scratchpad organization is described. Our experiments indicate that a multiretention STT-RAM scratchpad can provide energy savings of 53% with respect to an iso-area, hardware-managed SRAM cache

Dynamic model and control of a new quadrotor unmanned aerial vehicle with tilt-wing mechanism

In this work a dynamic model of a new quadrotor aerial vehicle that is equipped with a tilt-wing mechanism is presented. The vehicle has the capabilities of vertical take-off/landing (VTOL) like a helicopter and flying horizontal like an airplane. Dynamic model of the vehicle is derived both for vertical and horizontal flight modes using Newton-Euler formulation. An LQR controller for the vertical flight mode has also been developed and its performance has been tested with several simulations

Modeling and position control of a new quad-rotor unmanned aerial vehicle with tilt-wing mechanism

In this work a dynamic model of a new quadrotor aerial vehicle that is equipped with a tilt-wing mechanism is presented. The vehicle has the capabilities of vertical take-off/landing (VTOL) like a helicopter and flying horizontal like an airplane. Dynamic model of the vehicle is derived both for vertical and horizontal flight modes using Newton-Euler formulation. An LQR controller for the vertical flight mode has also been developed and its performance has been tested with several simulations

Affine Modeling of Program Traces

This is a post-peer-review, pre-copyedit version of an article published in IEEE Transactions on Computers. The final authenticated version is available online at: http://dx.doi.org/10.1109/TC.2018.2853747[Abstract] A formal, high-level representation of programs is typically needed for static and dynamic analyses performed by compilers. However, the source code of target applications is not always available in an analyzable form, e.g., to protect intellectual property. To reason on such applications it becomes necessary to build models from observations of its execution. This paper presents an algebraic approach which, taking as input the trace of memory addresses accessed by a single memory reference, synthesizes an affine loop with a single perfectly nested statement that generates the original trace. This approach is extended to support the synthesis of unions of affine loops, useful for minimally modeling traces generated by automatic transformations of polyhedral programs, such as tiling. The resulting system is capable of processing hundreds of gigabytes of trace data in minutes, minimally reconstructing 100 percent of the static control parts in PolyBench/C applications and 99.9 percent in the Pluto-tiled versions of these benchmarks.Ministerio de Economía y Competitividad; TIN2016-75845-PNational Science Foundation (Estados Unidos); 1626251National Science Foundation (Estados Unidos); 1409095National Science Foundation (Estados Unidos); 1439057National Science Foundation (Estados Unidos); 1213052National Science Foundation (Estados Unidos); 1439021National Science Foundation (Estados Unidos); 162912