Path loss modelling at 60 GHz mmWave based on cognitive 3D ray tracing algorithm in 5G

The objective of the study is to consider the foremost high-tech issue of mobile radio propagation i.e. path loss for an outdoor and indoor environment for mmWave in a densely populated area.60 [GHz] mmWave is a win-win for the 5th Generation radio network. Several measurements and simulations are performed using the simulator “Smart Cognitive 3D Ray Tracer” build in MATLAB. Two of the main parameters (pathloss and received signal strength (RSS)) of the radio propagation are obtained in this study. To compute the pathloss and RSS, 5G 3GPP mobile propagation model is selected due to its flexibility of scenario and conditions beyond 6 GHz frequency. For indoor simulations, we again chose 5G 3GPP mobile propagation model. It is evident from the recent previous studies that there is still not enough findings in the ray tracing specially cognitive 3D ray tracing. The suggested alternative cognitive algorithm here deals with less iterations and effective use of resources. The conclusions of this work also comprise that the path loss is reliant on separation distance of base station and receiver. The above mentioned frequency and interconnected distance reported here provide better knowledge of mobile radio channel attributes and can be also used to design and estimate the performance of the future generation (5G) mobile networks

A 79μW 0.24mm28-channel neural signal recording front-end integrated circuit

This brief presents a new architecture for an ultra-low power and area-efficient 8-channel prototype of a neural signal recording front-end circuitry. For implantable neural recording circuits, low power and low area are two of the most critical requirements. In contrast to architectures existing in the literature, the presented recording path is centered on a single high-performance programmable gain-bandwidth amplifier, instead of employing a separate stand-alone amplifier for each electrode. The resulting circuitry requires smaller area and less power compared to all previously published designs. Implemented in 0.5μm CMOS and a supply voltage of 1.8V, the 8-channel recording path is measured to consume a total of 79μW of power and a net area of 0.24mm 2 . Therefore, allowing suitability of our design to be used in high channel count environments