A General Formula for Impulse-Invariant Transformation for Continuous-Time Delta-Sigma Modulators

this paper presents a generalised new formula for impulse-invariant transformation which can be used to convert an nth-order Discrete-Time (DT) ΔΣ modulator to an nth-order equivalent Continuous-Time (CT) ΔΣ modulator. Impulse-invariant transformation formulas have been published in many open literature articles for s-domain to z-domain conversion and vice-versa. However, some of the published works contain omissions and oversights. To verify the newly derived formulas, very many designs of varying orders have been tested and a representative 4th-order single-loop DT ΔΣ modulator converted to an equivalent CT ΔΣ modulator through the new formulas are presented in this paper. The simulation results confirm that the CT ΔΣ modulator which has been derived by these formulas works in accordance with the initial DT specifications without any noticeable degradation in performance in comparison to its original DT ΔΣ modulator prototype

A 28mW 320MHz 3rd–Order Continuous-Time Time-Interleaved Delta-Sigma Modulator with 10MHz Bandwidth and 12 Bits of Resolution

this paper presents a 3rd-order two-path Continuous-Time Time-Interleaved (CTTI) delta-sigma modulator which is implemented in standard 90nm CMOS technology. The architecture uses a novel method to solve the delayless feedback path issue arising from the sharing of integrators between paths. The clock frequency of the modulator is 320MHz but integrators, quantizers and DACs operate at 160MHz. The modulator achieves a dynamic range of 12 bits over a bandwidth of 10MHz and dissipates only 28mW of power from a 1.8-V supply

Design of a Delayless Feedback Path Free 2nd-order Two-Path Time-Interleaved Discrete-Time Delta-Sigma Modulator- a New Approach

This paper presents the design procedure for a 2nd_order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator from a conventional single-loop 2nd-order Discrete-Time (DT) ΔΣ modulator through the use of time domain equations and time-interleaving concepts [1]. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue in Time-Interleaved (TI) ΔΣ modulators is a critical restriction for the implementation of TI ΔΣ modulators and is effectively eliminated through the use of the approach proposed in this paper. The DTTI ΔΣ modulator requires only three op-amps and two quantizers both of which work concurrently, in comparison to the single-loop DT counterpart that also deploys two op-amps. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 640MHz, our simulation results show a maximum Signal-to-Noise Ratio (SNR) for the DTTI ΔΣ modulator to be 70.5dB with an input bandwidth of 20MHz which has 15dB improvement in comparison to its single-loop, single-path DT counterpart

Design and Simulation of a 3rd-order Discrete-Time Time-Interleaved Delta-Sigma Modulator with Shared Integrators between Two Paths

This paper presents the design and simulation of a 3rd-order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator. By exploiting the concept of the time-interleaving techniques and time domain equations, a conventional 3rd-order Discrete-Time (DT) ΔΣ modulator is converted to a corresponding 3rd-order two-path DTTI counterpart. For the sake of saving power and silicon area, the integrators between the two paths of the DTTI ΔΣ modulator are shared. Using one set of integrators makes the DTTI ΔΣ modulator robust to path mismatch effects compared to the typical DTTI ΔΣ modulator which has individual integrators in all paths. A problem arises out of sharing integrators between paths which we call the delayless feedback problem. A solution for this problem is proposed in this paper and for an OverSampling Ratio (OSR) of 16 and a clock frequency of 320MHz, a maximum SNR of 76.5dB is obtained

Escaping Saddle Points with Adaptive Gradient Methods

Adaptive methods such as Adam and RMSProp are widely used in deep learning but are not well understood. In this paper, we seek a crisp, clean and precise characterization of their behavior in nonconvex settings. To this end, we first provide a novel view of adaptive methods as preconditioned SGD, where the preconditioner is estimated in an online manner. By studying the preconditioner on its own, we elucidate its purpose: it rescales the stochastic gradient noise to be isotropic near stationary points, which helps escape saddle points. Furthermore, we show that adaptive methods can efficiently estimate the aforementioned preconditioner. By gluing together these two components, we provide the first (to our knowledge) second-order convergence result for any adaptive method. The key insight from our analysis is that, compared to SGD, adaptive methods escape saddle points faster, and can converge faster overall to second-order stationary points.Comment: Update Theorem 4.1 and proof to use martingale concentration bounds, i.e. matrix Freedma

Stability analysis of higher-order delta-sigma modulators for sinusoidal inputs

The aim of this paper is to determine the stability of higher-order Δ-Σ modulators for sinusoidal inputs. The nonlinear gains for the single bit quantizer for a dual sinusoidal input have been derived and the maximum stable input limits for a fifth-order Chebyshev Type II based Δ-Σ modulators are established. These results are useful for optimising the design of higher-order Δ-Σ modulators