Near-thermal limit gating in heavily-doped III-V semiconductor nanowires using polymer electrolytes

Doping is a common route to reducing nanowire transistor on-resistance but has limits. High doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of sub-threshold swing and contact resistance that surpasses the best existing p-type nanowire MOSFETs. Our sub-threshold swing of 75 mV/dec is within 25% of the room-temperature thermal limit and comparable with n-InP and n-GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.Comment: 6 pages, 2 figures, supplementary available at journa

Effective g-factor in Majorana Wires

We use the effective g-factor of subgap states, g*, in hybrid InAs nanowires with an epitaxial Al shell to investigate how the superconducting density of states is distributed between the semiconductor core and the metallic shell. We find a step-like reduction of g* and improved hard gap with reduced carrier density in the nanowire, controlled by gate voltage. These observations are relevant for Majorana devices, which require tunable carrier density and g* exceeding the g-factor of the proximitizing superconductor. Additionally, we observe the closing and reopening of a gap in the subgap spectrum coincident with the appearance of a zero-bias conductance peak

Towards low-dimensional hole systems in Be-doped GaAs nanowires

GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly-confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately-doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly-doped nanowires and inability to reach a clear off-state under gating for the highly-doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio ~$10^{4}$, and sub-threshold slope 50 mV/dec at T = 4 K. Lastly, we made a device featuring a moderately-doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantization highlighting the potential for future quantum device studies in this material system

p-GaAs nanowire MESFETs with near-thermal limit gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$\Omega$, contact resistance ~30 k$\Omega$, peak transconductance 1.2 $\mu$S/$\mu$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance

Nonlocality of Majorana modes in hybrid nanowires

Spatial separation of Majorana zero modes distinguishes trivial from topological midgap states and is key to topological protection in quantum computing applications. Although signatures of Majorana zero modes in tunneling spectroscopy have been reported in numerous studies, a quantitative measure of the degree of separation, or nonlocality, of the emergent zero modes has not been reported. Here, we present results of an experimental study of nonlocality of emergent zero modes in superconductor-semiconductor hybrid nanowire devices. The approach takes advantage of recent theory showing that nonlocality can be measured from splitting due to hybridization of the zero mode in resonance with a quantum dot state at one end of the nanowire. From these splittings as well as anticrossing of the dot states, measured for even and odd occupied quantum dot states, we extract both the degree of nonlocality of the emergent zero mode, as well as the spin canting angles of the nonlocal zero mode. Depending on the device measured, we obtain either a moderate degree of nonlocality, suggesting a partially separated Andreev subgap state, or a highly nonlocal state consistent with a well-developed Majorana modeThis research was supported by Microsoft, the Danish National Research Foundation, the European Commission, and the Spanish Ministry of Economy and Competitiveness through Grants No. FIS2015-65706-P, No. FIS2015-64654-P, and No. FIS2016-80434-P (AEI/FEDER, EU), the Ramón y Cajal programme Grant No. RYC-2011-09345, and the María de Maeztu Programme for Units of Excellence in R&D (Grant No. MDM-2014-0377). C.M.M. acknowledges support from the Villum Foundation. M.-T.D. acknowledges support from State Key Laboratory of High Performance Computing, Chin

A Semiconductor Nanowire-Based Superconducting Qubit

We introduce a hybrid qubit based on a semiconductor nanowire with an epitaxially grown superconductor layer. Josephson energy of the transmon-like device ("gatemon") is controlled by an electrostatic gate that depletes carriers in a semiconducting weak link region. Strong coupling to an on-chip microwave cavity and coherent qubit control via gate voltage pulses is demonstrated, yielding reasonably long relaxation times (0.8 {\mu}s) and dephasing times (1 {\mu}s), exceeding gate operation times by two orders of magnitude, in these first-generation devices. Because qubit control relies on voltages rather than fluxes, dissipation in resistive control lines is reduced, screening reduces crosstalk, and the absence of flux control allows operation in a magnetic field, relevant for topological quantum information