Characterization of unitary processes with independent increments

In this paper, we study unitary Gaussian processes with independent increments with which the unitary equivalence to a Hudson-Parthasarathy evolution system is proved. This gives a generalization of results in [11] and [12] in the absence of the stationarity condition

CPU-GPU hybrid parallel binomial American option pricing

We present in this paper a novel parallel binomial algorithm that computes the price of an American option. The algorithm partitions a binomial tree constructed for the pricing into blocks of multiple levels of nodes, and assigns each such block to multiple processors. Each of the processors then computes the option's values at its assigned nodes in two phases. The algorithm is implemented and tested on a heterogeneous system consisting of an Intel multi-core processor and a NVIDIA GPU. The whole task is split and divided over and the CPU and GPU so that the computations are performed on the two processors simultaneously. In the hybrid processing, the GPU is always assigned the last part of a block, and makes use of a couple of buffers in the on-chip shared memory to reduce the number of accesses to the off-chip device memory. The performance of the hybrid processing is compared with an optimised CPU serial code, a CPU parallel implementation and a GPU standalone program.published_or_final_versio

Using web 2.0 tools to enhance learning in higher education: A case study in technological education

Pedagogy with Web 2.0 technologies is shown to facilitate the teaching-learning process through content sharing and idea collaboration. In this paper, we explore the possibility of using social networking tools, to support teaching practice in technological courses. In our study, we utilized i) Facebook Page as a platform to share content, experiences and news of a general engineering course, and ii) blog as a collaborative writing tool to express thoughts and opinions in a common core (general education) course. After our one-semester (three- months) study, we found that Facebook Page is an easy-to- use and familiar tool for students to share and exchange ideas among classmates, peers and public.published_or_final_versio

Dystocia and Foetal Mummification in A West African Dwarf Doe (A Case Report)

Nigerian Veterinary Journal, VOL:32 (4) 357-36

An In Vitro SEM Study on the Effectiveness of Smear Layer Removal of Four Different Irrigations

Introduction The aim of this study was to compare the smear layer removal efficacies of 3% sodium hypochlorite (NaOCl), 17% Ethylenediaminetetraacetic acid (EDTA), SmearClear and BioPure MTAD using a common irrigation protocol.Materials and Methods: Fifty freshly extracted human single rooted maxillary and mandibular teeth were prepared by a ProTaper rotary system up to an apical preparation file size F3. Prepared teeth were randomly divided into five groups (n=10); distilled water (Group A; negative control), EDTA (Group B), SmearClear (Group C), BioPure MTAD (Group D) and NaOCl (Group E). After final irrigation with tested irrigants the teeth were decoronated, split into two halves longitudinally and observed under a scanning electron microscope (SEM) for removal of the smear layer. The SEM images were then analyzed for the amount of smear layer present using a three score system. Data were analyzed using the Kruskal-Wallis test and Mann-Whitney U test.Results: Intergroup comparison of groups B, C, and D showed no statistical significant differences in the coronal and middle thirds, however, in the apical third the canal surfaces were cleaner in samples from group D (P<0.05).Conclusion: BioPure MTAD was the most effective agent for the purpose of smear layer removal in the apical third of the root canals

A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.published_or_final_versio