1,147 research outputs found
A Zero-Space algorithm for Negative Cost Cycle Detection in networks
AbstractThis paper is concerned with the problem of checking whether a network with positive and negative costs on its arcs contains a negative cost cycle. The Negative Cost Cycle Detection (NCCD) problem is one of the more fundamental problems in network design and finds applications in a number of domains ranging from Network Optimization and Operations Research to Constraint Programming and System Verification. As per the literature, approaches to this problem have been either Relaxation-based or Contraction-based. We introduce a fundamentally new approach for negative cost cycle detection; our approach, which we term as the Stressing Algorithm, is based on exploiting the connections between the NCCD problem and the problem of checking whether a system of difference constraints is feasible. The Stressing Algorithm is an incremental, comparison-based procedure which is as efficient as the fastest known comparison-based algorithm for this problem. In particular, on a network with n vertices and m edges, the Stressing Algorithm takes O(mā
n) time to detect the presence of a negative cost cycle or to report that none exists. A very important feature of the Stressing Algorithm is that it uses zero extra space; this is in marked contrast to all known algorithms that require Ī©(n) extra space. It is well known that the NCCD problem is closely related to the Single Source Shortest Paths (SSSP) problem, i.e., the problem of determining the shortest path distances of all the vertices in a network, from a specified source; indeed most algorithms in the literature for the NCCD problem are modifications of approaches to the SSSP problem. At this juncture, it is not clear whether the Stressing Algorithm could be extended to solve the SSSP problem, even if O(n) extra space is available
New Results on Cutting Plane Proofs for Horn Constraint Systems
In this paper, we investigate properties of cutting plane based refutations for a class of integer programs called Horn constraint systems (HCS). Briefly, a system of linear inequalities A * x >= b is called a Horn constraint system, if each entry in A belongs to the set {0,1,-1} and furthermore there is at most one positive entry per row. Our focus is on deriving refutations i.e., proofs of unsatisfiability of such programs using cutting planes as a proof system. We also look at several properties of these refutations. Horn constraint systems can be considered as a more general form of propositional Horn formulas, i.e., CNF formulas with at most one positive literal per clause. Cutting plane calculus (CP) is a well-known calculus for deciding the unsatisfiability of propositional CNF formulas and integer programs. Usually, CP consists of a pair of inference rules. These are called the addition rule (ADD) and the division rule (DIV). In this paper, we show that cutting plane calculus is still complete for Horn constraints when every intermediate constraint is required to be Horn. We also investigate the lengths of cutting plane proofs for Horn constraint systems
Kalman Filter Algorithm for Mitigation of Power System Harmonics
The maiden application of a variant of Kalman Filter (KF) algorithms known as Local Ensemble Transform Kalman Filter (LET-KF) are used for mitigation and estimation power system harmonics are proposed in this paper. The proposed algorithm is applied for estimating the harmonic parameters of power signal containing harmonics, sub-harmonics and inter-harmonics in presence of random noise. The KF group of algorithms are tested and applied for both stationary as well as dynamic signal containing harmonics. The proposed LET-KF algorithm is compared with conventional KF based algorithms like KF, Ensemble Kalman Filter (En-KF) algorithms for harmonic estimation with the random noise values 0.001, 0.05 and 0.1. Among these three noises, 0.01 random noise results will give better than other two noises. Because the phase deviation and amplitude deviation less in 0.01 random noise. The proposed algorithm gives the better results to improve the efficiency and accuracy in terms of simplicity and computational features. Hence there are less multiplicative operations, which reduce the rounding errors. It is also less expensive as it reduces the requirement of storing large matrices, such as the Kalman gain matrix used in other KF based methods
Integrin-mediated function of Rab GTPases in cancer progression
The RAS (rat sarcoma) superfamily of small GTPases is broadly subdivided into five groups: Ras, Rho, Rab, Ran, and Arf. Rab family proteins are important in regulating signal transduction and cellular processes such as differentiation, proliferation, vesicle transport, nuclear assembly, and cytoskeleton formation. However, some Rab proteins have been reported to be necessary for the adhesion and migration of cancer cells. Although Ras and Rho family members have been strongly implicated in cancer progression, knowledge of Rabs action in this regard is limited. Some reports have also linked Rab GTPases with cancer cell migration and invasiveness. This review discusses the implications of the involvement of Rabs in malignant transformation and cancer therapy through integrin-mediated signaling events, with particular emphasis on breast cancer
Performance analysis of PV powered multilevel inverter
This article deals with the PV based DC/DC boost chopper integrated nine level inverter. This topology requires 7 switches in minimum to obtain a nine level stepped wave output. So the main objective of this paper is to develop a 9 level AC output using PV based DC/DC boost chopper. In the case of conventional multi-level inverter, 16 switches were utilized and the number of sources needed was also more. Here the proposed system comprises of single PV panel and the switches used are also less. Also PV is integrated with DC/DC boost chopper is used to increase the source input level of the inverter. Using MATLAB platform, the proposed system is simulated with a resistive and inductive load. The similar results are obtained in prototype which validates the designed converter
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