166 research outputs found
A well of one's own: Gender analysis of an irrigation program in Bangladesh
Irrigation managementGroundwater irrigationGender differencesWomen in developmentPovertyHouseholdsAgricultural productionPrivatization
MoviCompile : An LLVM based compiler for heterogeneous SIMD code generation
Numerous applications in communication and multimedia domains show significant data-level parallelism (DLP). The amount of DLP varies between applications in the same domain or even within a single application. Most architectures support a single vector-, SIMD-width which may not be optimal. This may cause performance and energy inefficiency. We propose the use of multiple (heterogeneous) vector-widths to better serve applications with varying DLP. The SHAVE (Streaming Hybrid Architecture Vector Engine) VLIW vector processor shown in Figure 1 is an example of such an architecture. SHAVE is a unique VLIW processor that provides hardware support for native 32-bit (short) and 128-bit (long) vector operations. Vector arithmetic unit (VAU) supports 128-bit vector arithmetic of 8/16/32-bit integer and 16/32-bit floating point types. Scalar arithmetic unit (SAU) supports 32-bit vector arithmetic of 8/16-bit integer and 16-bit floating point types. The moviCompile compiler is an LLVM based commercial compiler targeting code generation for SHAVE processor family. The moviCompile compiler is capable of SIMD code generation for 128-bit (long) and 64-bit vector operations. This work focuses on compiler backend support for 32-bit (short) vector operations. More specifically, this work aims to generate SIMD code for short vector types (e.g. 4 x i8, 2 x i16, 2 x f16) that can be executed on 32-bit SAU next to the 128/64-bit SIMD code. As a result, moviCompile is able to generate heterogeneous assembly code consisting of both short and long vector SIMD operations. Currently, we are testing the compiler using TSVC (Test Suite for Vectorizing Compilers) and intend to measure the performance improvements
ASAM : Automatic Architecture Synthesis and Application Mapping; dl. 3.2: Instruction set synthesis
No abstract
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths
The degree of DLP parallelism in applications is not fixed and varies due to different computational characteristics of applications. On the contrary, most of the processors today include single-width SIMD (vector) hardware to exploit DLP. However, single-width SIMD architectures may not be optimal to serve applications with varying DLP and they may cause performance and energy inefficiency. We propose the usage of VLIW processors with multiple native vector-widths to better serve applications with changing DLP. SHAVE is an example of such VLIW processor and provides hardware support for the native 32-bit and 128-bit wide vector operations. This paper researches and implements the mixed-length SIMD code generation support for SHAVE processor. More specifically, we target generating 32-bit and 128/64-bit SIMD code for the native 32-bit and 128-bit wide vector units of SHAVE processor. In this way, we improved the performance of compiler generated SIMD code by reducing the number of overhead operations and by increasing the SIMD hardware utilization. Experimental results demonstrated that our methodology implemented in the compiler improves the performance of synthetic benchmarks up to 47%
Process evaluation of TeamUp: a movement-based psychosocial intervention for refugee children in the Netherlands
Adverse childhood experiences and global mental health: Avenues to reduce the burden of child and adolescent mental disorders
Adverse childhood experiences and global mental health: avenues to reduce the burden of child and adolescent mental disorders
Mental disorders are one of the largest contributors to the burden of disease globally, this holds also for children and adolescents, especially in low- and middle-income countries. The prevalence and severity of these disorders are influenced by social determinants, including exposure to adversity. When occurring early in life, these latter events are referred to as adverse childhood experiences (ACEs).In this editorial, we provide an overview of the literature on the role of ACEs as social determinants of mental health through the lenses of global mental health. While the relation between ACEs and mental health has been extensively explored, most research was centred in higher income contexts. We argue that findings from the realm of global mental health should be integrated into that of ACEs, e.g. through preventative and responsive psychosocial interventions for children, adolescents and their caregivers. The field of global mental health should also undertake active efforts to better address ACEs in its initiatives, all with the goal of reducing the burden of mental disorders among children and adolescents globally
Interventions for Children Affected by Armed Conflict: a Systematic Review of Mental Health and Psychosocial Support in Low- and Middle-Income Countries
- …