CMOS RF Power Amplifiers for Wireless Communications

The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals. The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology. The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated. The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals. The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion. The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB

Power Amplifier Circuits in CMOS Technologies

The wireless market has experienced a remarkable development and growth since the introduction of the first mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, a prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming significantly harder to meet the stringent requirements on linearity, output power, and power efficiency of PAs at lower supply voltages. This has recently triggered extensive studies to investigate the impact of different circuit techniques, design methodologies, and design trade-offs on functionality of PAs in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and highly efficient PAs and PA architectures in nanometer CMOS technologies at GHz frequencies. In total four PAs have been designed, two linear PAs and two switched PAs. Two PAs have been designed in a 65nm CMOS technology, targeting the 802.11n WLAN standard operating in the 2.4-2.5GHz frequency band with stringent requirements on linearity. The first linear PA is a two-stage amplifier with LC-based input and interstage matching networks, and the second linear PA is a two-stage PA with transformer-based input and interstage matching networks. Both designs were evaluated for a 72.2Mbit/s, 64-QAM 802.11n OFDM signal with a PAPR of 9.1dB. Both PAs fulfilled the toughest EVM requirement of the standard at average output power levels of 9.4dBm and 11.6dBm, respectively. Matching techniques in both PAs are discussed as well. Two Class-E PAs have been designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The first PA is intended for DECT, while the second is intended for Bluetooth. At 1.5V supply voltage and 1.85GHz, the DECT PA delivered +26.4dBm of output power with a drain efficiency (DE) and poweradded efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA had an output power of +22.7dBm at 1.0V with a DE and PAE of 48% and 36%, respectively, at 2.45GHz. The Class-E amplifier stage is also suitable for employment in different linearization techniques like Polar Modulation and Outphasing, where a highly efficient Class-E PA is crucial for a successful implementation

Linköping University Post Print A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS A 3.3V 72.2Mbit/s 802.11n WLAN Transformer- Based Power Amplifier in 65nm CMOS

Abstract-This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65nm CMOS technology. The PA utilizes 3.3V thick gate oxide (5.2nm) transistors and a twostage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6dBm and 19.6dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17dBm

A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS

This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.The original publication is available at www.springerlink.com:Jonas Fritzin and Atila Alvandpour, A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS, 2010, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (64), 3, 241-247.http://dx.doi.org/10.1007/s10470-009-9427-2Copyright: Springer Science Business Mediahttp://www.springerlink.com

Legalization of illegally obtained monetory resources as a type of criminal activity

Noziedzīgi iegūtu līdzekļu legalizēšana kā noziedzīga nodarījuma veids ir samērā jauns, tam ir aptuveni 20 gadus ilga vēsture. Tā ir aktuāla tēma, jo cieši saistīta ar ekonomisko situāciju valstī. Bakalaura darbs satur trīs nodaļas, kurās atspoguļota noziedzīgi iegūtu līdzekļu legalizēšanas attīstība, kriminālistiskā raksturojuma attīstība, paņēmieni, ar kādiem legalizē noziedzīgi iegūtus līdzekļus un paņēmienus, ar kādiem šos noziedzīgos nodarījumus atklāj. Noziedzīgi iegūtu līdzekļu legalizēšana šobrīd ir aktuāla tēma, jo tā ir cieši saistīta gan ar valsts amatpersonu dienesta stāvokļa ļaunprātīgu izmantošanu, pilnvaru pārsniegšanu, gan krāpšanu, izvairīšanos no nodokļu maksāšanas un dažāda veida noziegumiem, kas ar to saistīti. Jāapzinās, ka šāds nozieguma veids pastāv, attīstās un ir nepieciešams meklēt vispiemērotākās, efektīvākās metodes un paņēmienus, lai šādus noziedzīgus nodarījumus atklātu un ar sankciju palīdzību veicinātu šā nozieguma mazināšanos. Noziedzīgi iegūtu līdzekļu legalizēšana būtiski ietekmē valsts ekonomisko stāvokli, jo skaidrs, ka līdz ar šā nozieguma pastāvēšanu, pastāv arī „ēnu ekonomika”, līdz ar to valsts budžetā ieplūst daudz mazāk finanšu līdzekļu, nekā tam vajadzētu būt patiesībā. Nav iespējams procentuāli noteikt, cik liels tieši ir šis apmērs, kas neieplūst valsts budžetā, tomēr domājams, ka tas ir pietiekami nopietns, lai pamatīgi un efektīvi cīnītos pret šāda nozieguma izdarīšanu.Legalization of illegally obtained monetary resources as a type of criminal activity is rather new, its history runs about 20 years into the past. It is a topical issue because it is directly linked to the economic situation in the country. This bachelor paper consists of three chapters reflecting the development of legalization of illegally obtained monetary resources, development of the criminological description, ways to launder money as well as the techniques used to discover this type of crime. Legalization of illegally obtained monetary resources is a topical issue because it is directly linked to the abuse of state officials’ power as well as to breach of authority, fraud, tax evasion and various types of related criminal activity. We must be aware of the fact that this type of crime exists, it is developing, and the most applicable and efficient methods and techniques must be sought to discover these criminal acts as well as lead to a reduction of their scale with specific sanctions. Legalization of illegally obtained monetary resources drastically affects the economic state of the country because it is clear that, with the existence of this type of crime, there must also be a “shadow” economy, contributing much fewer funds to the state budget than actual facts would imply. It is impossible to specify accurately what percentage of the economy bypasses the state budget, although it is believed to be sufficiently serious for us to combat this type of crime earnestly and efficiently

A Review of Watt-Level CMOS RF Power Amplifiers

This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched watt-level PAs, as well as a few fully integrated CMOS PAs, is presented and discussed

A high-linearity SiGe RF power amplifier for 3G and 4G small basestations

This article presents the design and evaluation of a linear 3.3V SiGe power amplifier for 3G and 4G femtocells with 18dBm modulated output power at 2140 MHz. Different biasing schemes to achieve high linearity with low standby current were studied. The adjacent channel power ratio linearity performance with wide-band code division multiple access (3G) and long term evolution (4G) downlink signals were compared and differences analysed and explained

Learning Landscape Pastiche and Designing Book Covers in Home Economics and Technologies in Grade 9

Diplomdarba „Ainavas stilizācijas un grāmatu vāku izgatavošanas apguve 9. klasē mājturībā un tehnoloģijās” mērķis ir izpētīt ainavu stilizācijas un grāmatu vāku izgatavošanas apguves iespējas 9. klasē mājturībā un tehnoloģijās, izveidot mācību saturu un aprobēt to praksē. Diplomdarba izstrādes pedagoģiskā problēma ir mācību satura atlase un mācību tēmas sagatavošana. Diplomdarbā apkopota informācija par mācību satura atlasi, normatīvajiem dokumentiem, pusaudžu vecumposmu, mācību metodēm, vērtēšanu, uzskates līdzekļiem. Mācību satura izveidei apkopota informācija par grāmatu vāku veidošanu, tekstilmateriāliem un tehnikām, krāsu saskaņošanu, kompozīcijas veidiem, ainavu stilizāciju. Pētījumā izmantota literatūras un avotu analīze, aptauja un aprobācija praksē.Diploma ,,Learning Landscape Pastiche and Designing Book Covers in Home Economics and Technologies in Grade 9” aim is to explore opportunities of learning landscape pastiche and designing book covers in home economics and technologies in 9th grade, create content, thematic plan and approbate in practice. Diploma pedagogical problem is the development of learning content and trainings material preparation. Diploma summarizes the learning content selection, regulatory documents, teen age groups, teaching methods, evaluation, visual aids. Learning content creation contains information about the book cover designing, textiles and techniques, color matching, composition types, landscape pastiche. In the study is used the literature and source analysis, survey and approbation in practice