32 research outputs found
Required Repair Time to Assure the Given/Specified Availability
International audienceA novel, simple, easy-to-use, flexible and physically meaningful methodology is suggested for the assessment of the required repair/restoration time, so that the object's/system's availability is swiftly restored, thereby keeping this availability on the specified/desirable/required level during the entire time of the system's operation. A working table for the time-dependent availability function is obtained for the following two major governing input variables: 1) the product of the anticipated failure rate of the system of interest and the time of operation and 2) the ratio of the intensity of the restoration process to the meantime to failure (MTTF). This intensity is simply reciprocal to the mean time to repair (MTTR). The general concept is illustrated by a practical example. Several extensions of this work are considered and indicated, and particularly the role of the human-system interaction ("human-in-the-loop") situations, when system's reliability and human performance contribute jointly to the never-100%-failure-free operation process. _____________________________________________________________________________
A GestĂŁo Ativa da DĂvida PĂşblica
A presente dissertação tem como objetivo de estudo, compreender como Ă© feita a gestĂŁo da dĂvida pĂşblica, com especial atenção para a dĂvida pĂşblica portuguesa. Esta investigação foi feita com base nos relatĂłrios anuais publicados pela AgĂŞncia de GestĂŁo de Tesouraria e da DĂvida PĂşblica-IGCP, E.P.E e pelo Tribunal de Contas, nas guidelines para a gestĂŁo da dĂvida pĂşblica publicados pelo Fundo Monetário Internacional e Banco Mundial, e atravĂ©s de uma entrevista com o Dr. Jorge Guedes, colaborador da AgĂŞncia de GestĂŁo de Tesouraria e da DĂvida PĂşblica-IGCP, E.P.E.
Durante a dissertação procura-se mostrar quais os fatores a ter em conta para uma gestĂŁo eficiente da dĂvida pĂşblica, bem como a evolução que se tem verificado ao longo dos anos na gestĂŁo ativa da dĂvida pĂşblica portuguesa.
O saldo da dĂvida nos Ăşltimos anos cresceu significativamente e com isso a gestĂŁo da dĂvida foi tambĂ©m evoluindo, de forma a manter a dĂvida sustentável. As emissões reais seguiram sempre o benchmark definido, demonstrando que a gestĂŁo da dĂvida foi sempre feita tendo em consideração todos os limites de risco impostos pela tutela.
Em 2011 foi mesmo necessário assinar um acordo de ajuda externa (Programa de AssistĂŞncia EconĂłmica e Financeira), tendo a partir dessa data, a gestĂŁo ativa da dĂvida perdido importância, visto que nĂŁo dispomos de total autonomia para fazer as operações que se entendem convenientes.
Com este estudo constata-se que a gestĂŁo da dĂvida pĂşblica tem evoluĂdo de acordo com as condições macro-econĂłmicas e adaptando-se Ă conjuntura existente em cada momento.Esta dissertação permite observar a evolução de estratĂ©gias utilizadas na gestĂŁo da dĂvida ao longo dos Ăşltimos anos, bem como os valores atualizados respeitantes Ă s emissões de tĂtulos de dĂvida, Ă evolução do saldo da dĂvida e respetivos encargos
Nanostructured SnO2 thick films for gas sensor application: analysis of structural and electronic properties
This research is focused on structural and electrical characterisation of tin oxide (SnO2) applied as a thick film and investigation of its properties as gas sensitive material. Micron sized SnO2 powder was milled in an agate mill for six hours to fabricate SnO2 nanopowder, which was afterwards sieved by 325 mesh sieve and characterized by XRD and SEM. This powder was used as functional part in the production of thick film tin oxide paste containing a resin vehicle with 4 wt. % nanosize glass frits acting as permanent binder. The glass frits where additionally milled for twelve hours in the agate mills to nanosized powder and sieved by a 325 mesh sieve as well. The achieved thick film paste was screen printed on alumina and fired at 850oC peak temperature for 10 minutes in air. After the sintering process, thick film samples where characterized by X-ray powder diffraction (XRD) and scanning electron microscopy (SEM). The reflectivity was measured on the same samples by UV-VIS spectrophotometer: the band gap was determined from the slope of reflectance. After that a matrix of different interdigitated electrode structure of PdAg paste was printed and sintered using the mentioned sintering conditions. The tin oxide thick film was printed over the interdigitated electrodes as a top layer and sintered again under the same conditions. The total electrical resistance was measured as a function of the electrode spacing and temperature. A negative temperature coefficient (NTC) was identified and measured in the range from room temperature (27°C) to 180°C in a climate chamber. Finally the samples were placed into a gas reactor with NOx and CO gas and the resistance was measured in the same temperature range (27°C-200°C)
Predicted Stresses in Ball-Grid-Array (BGA) and Column-Grid-Array (CGA) Interconnections in a Mirror-Like Package Design
There is an obvious incentive for using bow-free (temperature change insensitive) assemblies in various areas of engineering, including electron device and electronic packaging fields. The induced stresses in a bow-free assembly could be, however, rather high, considerably higher than in an assembly, whose bow is not restricted. The simplest and trivial case of a bow-free assembly is a tri-component body, in which the inner component is sandwiched between two identical outer components (“mirror” structure), is addressed in our analysis, and a simple and physically meaningful analytical stress model is suggested. It is concluded that if acceptable stresses (below yield stress of the solder material) are achievable, a mirror (bow-free, temperature-change-insensitive) design should be preferred, because it results in an operationally stable performance of the system
Could Application of Column-Grid-Array (CGA) Technology Result in Inelastic-Strain-Free State-of-Stress in Solder Material?
Physically meaningful and easy-to-use analytical stress model is developed for a short cylinder (beam) clamped at the ends and subjected to bending caused by the ends offset. The offset is due, in its turn, to an external lateral force that has to be determined from the known offset. It is envisioned that such a beam can adequately represent the state of stress in a column-grid-array (CGA) solder joint interconnection experiencing thermal loading due to the thermal expansion/contraction mismatch of the IC package and the printed circuit board (PCB). The CGA designs are characterized by considerably higher stand-off heights than ball-grid-array (BGA) systems. The offset Δ = lΔαΔt for a CGA solder joint located at the distance l from the mid-cross-section of the package/PCB assembly (the neutral point (DNP)), can be determined, in an approximate analysis, as a product of this distance and the “external” thermal mismatch strain ΔαΔt between the IC package and the printed circuit board (PCB). Here Δα is the difference in the effective coefficients of thermal expansion (CTE) of the PCB and package materials, and Δt is the change in temperature. The objective of the analysis is to demonstrate that the application of a CGA design, in which the solder joints are configured as short clamped–clamped beams, enables one not only to significantly relieve the thermally induced stresses, compared to the BGA system, but possibly to do that to an extent that the stresses in the solder material would remain within the elastic range. If this is achieved, the low-cycle-fatigue condition for the solder material will be replaced by the elastic-fatigue condition, thereby leading to a significantly longer fatigue lifetime of the joint. The elastic fatigue lifetime can be assessed, as is known, based on the Palmgren–Miner rule of linear accumulation of damages. Our analysis is limited therefore to elastic deformations
Power core (PC) Embedding a Plurality of IC Devices and Sandwiched Between Two Dissimilar Insulated Metal Substrates (IMS’): Predicted Thermal Stresses
Power core (PC) sandwiched between two insulated metal substrates (IMS) and embedding active and passive integrated circuit (IC) devices is currently viewed as an attractive advanced packaging option having a strong potential in the automotive industry and beyond. A natural reliability concern, however, is the level of the thermally induced stresses in a tri-material assembly of the type in question. Accordingly, an analytical (mathematical) stress model is developed for the evaluation of these stresses. The stresses include normal stresses acting in the cross-sections of the assembly components, and the interfacial shearing and peeling stresses acting at the interfaces of these components and at the interfaces of the embedded IC devices. The model can be helpful in the stress-analysis and physical design of the assemblies, in which the PC is sandwiched between two IMS’. It can be used also in other areas of engineering, where tri-material assemblies comprised of dissimilar materials and subjected to the change in temperature are employed. The general concepts are illustrated by a detailed numerical example. The analysis is an extension of the study carried out earlier for a bow-free assembly. It is noteworthy that although the calculations are carried out for the case when the assembly is cooled down from an elevated temperature to a low temperature, since a linear approach is used and the stresses are proportional to the change in temperature, whatever its sign or the magnitude is, the developed model is equally applicable to any change in temperature
High resolution thermal simulation of electronic components
An efficient thermal management in electronic components is essential to minimize the influence of thermomechanically induced stress and thermal load. Frequently, thermal simulation tools are applied to reduce the number of experiments needed for thermal characterization of the semiconductor components. However, for using commercially available software packages, much effort is necessary for maintenance and for generating the thermal models. Moreover, the limitation of the node number does not allow a discretization sufficiently fine for more complex structures as in high lead count packages. In this paper, a new thermal simulation tool is presented, which allows one to create models in a very efficient way. The developed and implemented solver based on the alternating direction implicit method is efficiently processing the required high node number. Moreover, the developed thermal simulation tool is applied for the thermal characterization of a 176 lead quad flat pack (QFP-package) using a discretization with 320,000 nodes. Steady-state and transient thermal qualities of the package are investigated under boundary conditions as specified by the Joint Electronic Device Engineering Council (JEDEC). Further, results obtained by thermal simulation are compared with those established from experimental procedures. Conclusions of how this new tool can be used for thermal design optimization are derived
Semiconductor Film Grown on a Circular Substrate: Predictive Modeling of Lattice-Misfit Stresses
effective and physically meaningful analytical predictive model is developed for the evaluation the lattice-misfit stresses (LMS) in a semiconductor film grown on a circular substrate (wafer). The two-dimensional (plane-stress) theory-of-elasticity approximation (TEA) is employed in the analysis. The addressed stresses include the interfacial shearing stress, responsible for the occurrence and growth of dislocations, as well as for possible delaminations and the cohesive strength of a buffering material, if any. Normal radial and circumferential (tangential) stresses acting in the film cross-sections and responsible for its short- and long-term strength (fracture toughness) are also addressed. The analysis is geared to the GaN technology
Bow-Free Electronic Assembly: Predicted Stresses in Its Components and Embedded Devices
International audienc
Predicted Device-Degradation Failure-Rate
There is a concern that the continuing trend on miniaturization (Moore\u27s law) in IC design and fabrication might have a negative impact on the device reliability. To understand and to possibly quantify the physics underlying this concern and phenomenon, it is natural to proceed from the experimental bathtub curve (BTC) - reliability “passport” of the device. This curve reflects the combined effect of two major irreversible governing processes: statistics-related mass-production process that results in a decreasing failure rate with time, and reliability-physics-related degradation (aging) process that leads to an increasing failure rate. It is the latter process that is of major concern of a device designer and manufacturer.
The statistical process can be evaluated theoretically, using a rather simple predictive model. Owing to that and assuming that the two processes of interest are statistically independent one can assess the failure rates associated with the aging process from the BTC data by simply subtracting the predicted ordinates of the statistical failure rates (SFR) from the BTC ordinates. The objective of this analysis is to show how this could be done.
The suggested methodology proceeds from the concepts that the actual (“instantaneous”) SFR is a random variable with a known (assumed, established) probability distribution, that the experimental BTC can be represented by its infant mortality and the wear-out portions only (the steady-state portion in this case is simply the boundary between the infant mortality and wear-out portions) and that the two BTC portions considered can be approximated analytically. The cases, when the “instantaneous” SFR is distributed normally and in accordance with the Rayleigh law are used as suitable illustrations of the general concept.
The developed methodology can be employed when there is a need to better understand the relative roles of the statistics-related and physics-of-failure-related processes in reliability evaluations of electronic products. The methodology can be used also beyond the field of IC engineering, when there is a need to understand and, hence, to separate the roles of the two irreversible processes in question.
One of the major challenges of the future work is to determine the probability distributions of the actual (“instantaneous”) SFRs for particular products and applications